Lam Research Corporation

William Frederick Bosch

Helen H Zhu

Tamarak Pandhumsoporn

Syed A Haider

Brett C Richardson

Rao Annapragada

James C Vetter

Patrick Chung

Alferd Cofer

Rajesh Dorai

Stephen Anthony Dynan

Marc David Shull

An edge ring assembly is provided, including: an upper edge ring configured to surround an electrostatic chuck (ESC), the ESC having a top surface for supporting a substrate and an annular step surrounding the top surface, the annular step defining an annular shelf that is lower than the top surface, the upper edge ring being disposed above the annular shelf; a lower inner edge ring disposed below the upper edge ring in the annular step and disposed over the annular shelf, the lower inner edge ring being defined from an electrically conductive material, the lower inner edge ring being electrically insulated from the ESC; a lower outer edge ring surrounding the inner edge ring, the lower outer edge ring being disposed below the upper edge ring in the annular step and disposed over the annular shelf, the lower outer edge ring being defined from an electrically insulating material.

Edge ring assembly for improving feature profile tilting at extreme edge of wafer

Vaporizer

A ceramic part having a surface exposed to the interior space, the surface having been shaped and plasma conditioned to reduce particles thereon by contacting the shaped surface with a high intensity plasma. The ceramic part can be made by sintering or machining a chemically deposited material. During processing of semiconductor substrates, particle contamination can be minimized by the ceramic part as a result of the plasma conditioning treatment. The ceramic part can be made of various materials such as alumina, silicon dioxide, quartz, carbon, silicon, silicon carbide, silicon nitride, boron nitride, boron carbide, aluminum nitride or titanium carbide. The ceramic part can be various parts of a vacuum processing chamber such as a liner within a sidewall of the processing chamber, a gas distribution plate supplying the process gas to the processing chamber, a baffle plate of a showerhead assembly, a wafer passage insert, a focus ring surrounding the substrate, an edge ring surrounding an electrode, a plasma screen and/or a window.

Semiconductor processing equipment having improved particle performance

A method for etching silicon layer of a substrate, which is deposited on a bottom electrode in a plasma processing chamber. The method includes performing a main etch step until at least 70 percent of silicon layer is etched. The method further includes an overetch step, which includes a first, second, and third process steps. The first process step employs a first process recipe, the second process step employs a second process recipe, and the third process step employs a third process recipe. The second process recipe employs a second bottom bias voltage level applied to the bottom electrode which is higher than the first bottom bias voltage level employs in the first process recipe and the third bottom bias voltage level employs in the third process recipe. The first, second, and third process steps are alternated a plurality of times until silicon layer is etched through.

Methods for minimizing mask undercuts and notches for plasma processing system

Process for etching features in wafers incorporating OSG dielectrics. The process results at once in minimal RIE lag, minimal bowing of the features formed by the etch process, good etch profiles, good resist selectivity, and good etch uniformity across the wafer. In order to provide these desirable results, a novel etch gas mixture, including CH2F2 and CF4 is employed. According to one embodiment of the present invention, this novel gas mixture is employed as part of a three-step etch process wherein the several etch steps have varying degrees of etch selectivity between wafer components. The methodology of the present invention is capable of implementation on a wide variety of existing semiconductor etch equipment.

Process for etching vias in organosilicate glass materials without causing RIE lag

A ceramic part having a surface exposed to the interior space, the surface having been shaped and treated to reduce particles thereon by formation of an oxide layer on the surface in which particles produced by shaping are incorporated in the oxide layer optionally followed by stripping the oxide layer. The ceramic part can be made by machining a surface of the ceramic part and oxidizing the surface such that particles produced by the machining are incorporated in an oxide layer on the surface. The oxide layer can be chemically stripped to remove the oxide layer with the particles incorporated therein. During processing of semiconductor substrates, particle contamination can be minimized by the ceramic part as a result of incorporating the particles in the oxide layer or as a result of removing the oxide layer. The ceramic part can be made of various materials such as carbon, silicon, silicon carbide, silicon nitride, boron nitride, boron carbide, aluminum nitride or titanium carbide. The ceramic part can be various parts of a vacuum processing chamber such as a liner within a sidewall of the processing chamber, a gas distribution plate supplying the process gas to the processing chamber, a baffle plate of a showerhead assembly, a wafer passage insert, a focus ring surrounding the substrate, an edge ring surrounding an electrode, a plasma screen and/or a window.

A dry etching process for use in the manufacture of silicon integrated circuit devices uses a mixture of about eight parts neon to one part CHF.sub.3 (Freon 23) to form the etching plasma. The process etches doped oxides of silicon, such as BPSG and BPTEOS, in preference to undoped oxides of silicon, silicon nitride, silicides and silicon.

Growing community of inventors

Fremont, CA, United States of America

William Frederick Bosch