Rambus Inc.

Other

William Franklin Stonecypher

Jared L Zerbe

Michael Tak-Kei Ching

Andy Peng-Pui Chan

Pak Shing Chau

Billy Wayne Garrett, Jr

Matthew Murdy Griffin

Carl William Werner

John Bradly Dillon

Mark A Horowitz

Richard Maurice Barth

Robert E Palmer

Paul G Davis

Abhijit Mukun Abhyankar

Anthony G Bessios

Nancy David Dillon, Legal Representative

Dennis Kim

Scott C Best

Fred F Chen

Haw-Jyh Liaw

Barry William Daly

Andrew M Fuller

Timothy Chang

Nancy David Dillon

John B Dillon, Deceased

By Nancy David Dillon

Amita Agarwal

A latency controller within an integrated circuit device retimes command-stream-triggered control and timing signals into endpoint timing domains having respective time-varying phase offsets relative to a reference clock by iteratively estimating and logging the phase offsets independently of commands streaming into the integrated circuit device.

Low-power multi-domain synchronizer

A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Method and apparatus for evaluating and optimizing a signaling system

In a memory controller having a controller core and a physical signaling interface, the controller core outputs a request for read data to the physical signaling interface specifying one of at least two memory components from which the read data is to be retrieved. In response to the request for read data, the physical signaling interface outputs a memory read request to the specified memory component, receives the read data from the specified memory component, and transfers the read data to the controller core at either a first time or a second time according to whether the specified memory component is a first memory component or second memory component of the at least two memory components.

Memory controller with dynamic core-transfer latency

A memory controller that extends the window when reading data from the memory device to compensate for fluctuations in a read strobe delay. The memory controller includes a communication port that receives a timing reference signal for reading data from a memory device. A control circuit generates a gating signal indicative of a read window. A gating adjustment circuit generates an adjusted gating signal indicative of an adjusted read window based on the gating signal and the timing reference signal. A gating circuit generates a first gated timing reference signal for reading data by gating a delayed version of the timing reference signal with the adjusted gating signal.

Read strobe gating mechanism

A circuit, apparatus and method obtains system margin at the receive circuit using phase shifted data sampling clocks while allowing the CDR to remain synchronized with the incoming data stream in embodiments. In an embodiment, a circuit includes first and second samplers to sample a data signal and output data and edge information in response to a data clock signal and an edge clock signal. A phase detector generates phase information in response to the data information and the edge information. A clock phase adjustment circuit generates the data clock signal and the edge clock signal in response to the data information during a synchronization mode. The clock phase adjustment circuit increments a phase of the data clock signal during a waveform capture mode.

Circuit, apparatus and method for capturing a representation of a waveform from a clock-data recovery (CDR) unit

An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (), an analog voltage divider (), an input comparator (), a sampling latch (), a current control counter (), and a bitwise output driver (output driver Aand output driver B).

Current control technique

Provided are a method and apparatus for high-speed, multi-mode PAM symbol transmission. A multi-mode PAM output driver drives one or more symbols, the number of levels used in the PAM modulation of the one or more symbols depending on the state of a PAM mode signal. Additionally, the one or more symbols are driven at a symbol rate, the symbol rate selected in accordance with the PAM mode signal so that a data rate of the driven symbols is constant with respect to changes in the state of the PAM mode signal. Further provided are methods for determining the optimal number of PAM levels for symbol transmission and reception in a given physical environment.

Transparent multi-mode PAM interface

A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.

Method and apparatus for fail-safe resynchronization with minimum latency

Growing community of inventors

San Jose, CA, United States of America

William Franklin Stonecypher