International Business Machines Corporation

William F Washburn

Louis L Hsu

Michael Anthony Sorna

Brian L Ji

Karl David Selander

Joseph Natonio

Daniel W Storaska

John E Campbell

Steven John Zier

Huihao Xu

William T Devine

Charles H Milligan

Michael James Chan

Steven F Hajek

Roy A Wood

George A Williams, Ii

Frank A Almquist

Cyril A Price

Andrew M Simon

John F Larsen

Stephen W Flaherty

David F Anderson

As disclosed herein, a microelectronic circuit and method are provided for improving signal integrity at a transmission line. The circuit includes a programmably adjustable impedance matching circuit which is coupled to a transmission line which includes a programmably adjustable inductive element. The programmably adjustable impedance matching circuit is desirably provided on the same chip as a receiver or transmitter to which the transmission line is coupled, or alternatively, on an element packaged together with the chip that includes the receiver or transmitter. The impedance of the programmably adjustable impedance matching circuit is adjustable in response to control input to improve signal integrity at the transmission line.

Programmable impedance matching circuit and method

A data transmitter and transmitting method are provided in which an adaptive finite impulse response (FIR) driver has a plurality of taps to which coefficients having updateable values are applied. The FIR driver has a transfer function between an input stream of data bits and an output stream of data bits such that each data bit output from the FIR driver has an amplitude adjusted as a function of the values of a plurality of data bits of the input stream, and the values of the coefficients. The data transmitter includes a rewriteable non-volatile storage, operable to be rewritten with control information representing the values of the coefficients updated during operation of the FIR driver.

Adaptive data transmitter having rewriteable non-volatile storage

Methods and structures are disclosed herein for programmably adjusting a peaking function of a differential signal receiver. The disclosed method includes inputting a pair of differential signals to a pair of input transistors coupled to conduct currents differentially between a pair of load impedances and a pair of tail transistors. The impedance of an adjustable shunt impedance element between the tail transistors of the receiver is varied by programming signal input, such that higher current is conducted over a peaking range of frequencies. In a disclosed structural embodiment, an integrated circuit is provided having a programmable peaking receiver. The programmable peaking receiver includes a pair of input transistors coupled to conduct differentially according to a pair of differential inputs applied to the pair of input transistors. Each of the input transistors produces an output in accordance with the differential input applied thereto. The programmable peaking receiver also includes a pair of tail transistors, coupled to draw current from the input transistors, and a programmably adjustable impedance element coupled between current-conducting nodes of the tail transistors. The impedance of the programmably adjustable impedance element is thereby adjustable in response to programming signal input to adjust a peaking function of the programmable peaking receiver.

Programmable peaking receiver and method

A method and system are disclosed for selectively altering the functional characteristics of a data processing system without physical or mechanical manipulation. A data processing system is first manufactured having a predetermined set of functional characteristics. A multibit alterable code which includes a functional characteristic definition is then initially loaded into physically secure, nonvolatile memory within the data processing system, utilizing an existing bus, or a fusible link which may be opened after loading is complete. The functional characteristic definition is loaded from nonvolatile memory into a nonscannable register within a secure portion of a control logic circuit each time power is applied to the data processing system and the definition is then utilized to enable only selected functional characteristics. Alternate functional characteristics may thereafter be selectively enabled by entering a security code which matches one of a number of preloaded codes and an encoded alternate functional characteristic definition. The alternate functional characteristic definition may be enabled on a one-time, metered, or regularly scheduled basis and variable capability data processing systems may be implemented in this manner utilizing a single manufactured system, without the necessity of manufacturing and storing multiple data processing system models.

Method and system for selectively altering data processing system

An improved logical OR circuit is shown wherein the load resistance is divided into drain resistance and source resistance, each resistance having a lower value than could be employed with a single load resistance while at the same time keeping power dissipation to low levels. The use of relatively lower resistances permits faster voltage rise time, thereby permitting faster programmed logic array (PLA) operation. The voltage drop across the source resistance is made small when the output device is conducting by providing a substantially higher drain resistance load for the output device with respect to the drain resistance of the input devices.

Logical OR circuit for programmed logic arrays

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Hyde Park, NY, United States of America

William F Washburn