Texas Instruments Corporation

Other

Micron Technology Incorporated

William F Richardson

Robert R Doering

Siang Ping Kwok

Bing W Shen

Satwinder S Malhi

Dirk N Anderson

Gordon P Pollack

Yin Hu

William R McKee

Rick L Wise

Clarence W Teng

Pallab K Chatterjee

Lionel S White, Jr

Darius Lammont Crenshaw

Ashwin H Shah

Gishi Chung

Donald M Bordelon

Anhkim Duong

Jiann Liu

Mark Bordelon

Yuji Sasaki

In one aspect, the invention encompasses a method of forming a capacitor. A mass is formed over an electrical node. An opening is formed within the mass. The opening has a lower portion proximate the node and an upper portion above the lower portion. The lower portion is wider than the upper portion. A first conductive layer is formed within the opening and along a periphery of the opening. After the first conductive layer is formed, a portion of the mass is removed from beside the upper portion of the opening while another portion of the mass is left beside the lower portion of the opening. A dielectric material is formed over the first conductive layer, and a second conductive layer is formed over the dielectric material. The second conductive layer is separated from the first conductive layer by the dielectric material. In another aspect, the invention encompasses a capacitor construction.

Capacitor constructions

A post-in-crown capacitor is disclosed. The post-in-crown capacitor ( ) includes a crown ( ) coupled to a conductive via ( ). A post ( ) is disposed within the crown ( ) and a capacitor insulation layer ( ) is formed outwardly from the crown ( ) and the post ( ). A capacitor plate layer ( ) is then formed outwardly from the capacitor insulation layer ( ).

Post-in-crown capacitor and method of manufacture

Methods of forming capacitors

A low resistance bipolar transistor extrinsic base and method of manufacture. A layer of heavily doped polysilicon is deposited over an oxide layer on an npn silicon substrate and a window is formed through to an n doped region of the substrate. Epitaxial SiGe is grown on the polysilicon layer and within the window. Dopant from the polysilicon layer diffuses into the SiGe layer thereby lowering its resistance.

SiGe/poly for low resistance extrinsic base npn transistor

The stress at the edges of a thin film conductor can be reduced by noncoincident layered structures, which takes advantage of the characteristic stress polarity changing from tensile to compressive or vice versa in the edge vicinity in order to avoid device reliability and performance problems. By using noncoincident layered structures, destructive stress interference from different layers can be achieved to reduce the stress or stress gradient at the edge. The structures and methods disclosed herein can advantageously be used in many integrated circuit and device manufacturing applications (including gates, wordlines, and bitlines).

Edge stress reduction by noncoincident layers

A method of fabricating a semiconductor device and the device which includes initially providing a layer of silicon having a thin oxide layer thereon and a patterned layer of a masking material not permeable to at least selected oxygen-bearing species and having a sidewall disposed over said oxide layer to provide an exposed intersection of the masking material and the oxide layer. An oxygen-bearing species conductive path is then formed on the sidewall of the masking material extending to the exposed intersection for conducting the selected oxygen-bearing species. A sidewall layer of a material different from the conductive path is formed on the conductive path. An oxygen-bearing species is then applied to the exposed intersection through the path and a thick oxide surrounding the masking material is fabricated concurrently or as a separate step. The masking material is preferably silicon nitride, the path is preferably silicon oxide and the sidewall layer is preferably silicon nitride.

Oxide profile modification by reactant shunting

A method is disclosed for reproducibly and controllably enhancing the current gain of a bipolar junction transistor. Prior to depositing an extrinsic emitter region of polycrystalline silicon, the surface of a monocrystalline silicon substrate is nitridized to grow a layer of silicon nitride thereon. The interfacial layer of silicon nitride functions as a tunnel insulator to enhance the current gain of the transistor and as a diffusion barrier to prevent thickening of the tunnel insulator due to the growth of a native oxide layer while exposed to an oxygen-containing atmosphere. The ubiquitous native silicon oxide on the surface of the monocrystalline silicon substrate may be optionally removed either before nitridation or after nitridation.

Tunnel nitride for improved polysilicon emitter

A semiconductor device (60) may comprise a semiconductor layer (12) having an outer surface (20). A plurality of gates (18) may be disposed over the outer surface (20) of the semiconductor layer (12). An isolation cover (30) may be disposed over the gates (18). An implant screen (40) may be grown on the outer surface (20) of the semiconductor layer (12) between the isolation covers (30) of the gates (18).

Implant screen and method

A dRAM memory cell structure and a method for forming the same is disclosed. Each memory cell is formed at a pillar, where the storage plate is an inversion region created by a field plate surrounding all sides of each pillar and separated therefrom by a storage dielectric film. The field plate is formed in a grid shape, and is disposed at the bottom of the trenches surrounding the array of pillars to serve as the fixed plate for all storage capacitors in the array. At the top of each pillar is a diffusion to which the bit lines are connected. Disposed in the trench above the field plate and extending in one direction are word lines. Each word line is formed of a polysilicon filament onto which tungsten is deposited by way of selective CVD. The word line is formed closely adjacent the pillars in its associated row, separated therefrom by a gate dielectric film; the word line is separated from the adjacent row by a dielectric film which is thicker than the gate dielectric, so that the word line will cause conduction between the inversion region and the top diffusion for its associated row, but not for the adjacent row.

High performance composed pillar dRAM cell

A DRAM memory cell structure and a method for forming the same is disclosed. Each memory cell is formed at a pillar, where the storage plate is an inversion region created by a field plate surrounding all sides of each pillar and separated therefrom by a storage dielectric film. The field plate is formed in a grid shape, and is disposed at the bottom of the trenches surrounding the array of pillars to serve as the fixed plate for all storage capacitors in the array. At the top of each pillar is a diffusion to which the bit lines are connected. Disposed in the trench above the field plate and extending in one direction are word lines. Each word line is formed of a polysilicon filament onto which tungsten is deposited by way of selective CVD. The word line is formed closely adjacent the pillars in its associated row,, separated therefrom by a gate dielectric film; the word line is separated from the adjacent row by a dielectric film which is thicker than the gate dielectric, so that the word line will cause conduction between the inversion region and the top diffusion for its associated row, but not for the adjacent row.

High performance composed pillar DRAM cell

By placing boundary cells within areas of discontinuity of a memory array, such as in word line strap areas, stress on edge cells of the memory array is reduced; the reduction of stress improves leakage characteristics and pause-refresh capabilities of edge cells. The boundary cells may further be laid out in the areas of discontinuity with the same pattern as the memory array. Some of the boundary cells may be electrically biased to act as minority carrier sinks. By collecting minority carriers that otherwise may be attracted to edge cells of the memory array, the leakage characteristics of the edge cells and their pause-refresh capabilities are further enhanced. The boundary cells are particularly useful in improving leakage characteristics of dynamic random access memory devices of the trench capacitor type.

Boundary cells for improving retention time in memory devices

A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with both the transistor and the capacitor formed in a trench in a substrate. The transistor source, channel and drain and one capacitor plate are formed essentially vertically in the bulk substrate sidewalls of the trench, and the gate and other capacitor plate are formed in two regions of material inserted into the trench and isolated from the bulk by an insulating layer. Signal charge is stored on the capacitor material inserted into the trench by an electrical connection of the bulk substrate source to the capacitor material through the insulating layer. In preferred embodiments word lines on the substrate surface connect to the upper of the inserted regions which forms the gate, and bit lines on the substrate surface form the drains. The trenches and cells are formed at the crossings of bit lines and word lines; the bit lines and the word lines form perpendicular sets of parallel lines.

dRAM cell and method

A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with the capacitor formed in a trench in a substrate and the transistor channel formed by epitaxial growth on the substrate. The transistor source and drain are insulated from the substrate, and the transistor may be adjacent the trench or on the upper portion of the trench sidewalls. Signal charge is stored on the capacitor plate insulated from the substrate.

Growing community of inventors

Richardson, TX, United States of America

William F Richardson