International Business Machines Corporation

William F Pokorny

Terence B Hook

Mark Alan Lavin

Paul Steven Zuchowski

Patrick Edward Perry

Jeffrey Scott Zimmerman

Alan L Roberts

William John Livingstone

Henry A Bonges, Iii

Jeannie H Panner

Young O Kim

Robert T Sayah

Laura R Darden

Geordie M Braceras

Phillip L Corson

Jason M Parry

Gary R Holsopple

A method and system for validating a design rule checking program. The method and system includes creating a hierarchal structure such that each layer of the hierarchal structure corresponds to a process layer of a device or subregion of a shape. The method and system further includes inserting the created hierarchical structure into a DRC program and running the DRC program at least once with hierarchical optimization options turned off. The method and system compares the expected results with actual results. The differences between the expected results and the actual results actual results indicate errors in the DRC program.

Method and system of introducing hierarchy into design rule checking test cases and rotation of test case data

A method is disclosed of determining allowable antenna limits for semiconductor-on-insulator (SOI) technology. In one embodiment, the method may include: determining antenna area on a gate; determining antenna area on a source/drain; determining a total gate insulator area between gate and source/drain nets; and calculating allowable antenna area as a function of the total gate insulator area between the nets such that a larger total antenna area is allowed for larger total gate insulator area between the nets.

Determining allowance antenna area as function of total gate insulator area for SOI technology

A method and system for identifying problematic areas in a very large scale integrated (VLSI) layout. The method and system includes defining one or more sample area and overlaying the one or more sample area onto at least a portion of a layout having a plurality of structures. The method and system includes identifying at least one region of the layout in the sample area which has at least one structure which satisfies a predetermined value. In embodiments, the method and system can be implemented on a computer program product comprising a computer useable medium including a computer readable program.

Method and apparatus of rapid determination of problematic areas in VLSI layout by oriented sliver sampling

High resolution gray scale graphical images are formed in a semiconductor substrate by the use of two or more levels of indicia having a plurality of image segments and having a continuous conductive line formed in the surface of the substrate, each image segment includes a portion of said continuous conductive line and a contrasting material providing pixels in which the width of the line within a segment varies in relationship to gray scale levels in the graphic image to be formed. Providing a graphic image to be converted; converting the graphic image to a gray level, two dimensional bit mapped converting the bit mapped image into a set of parallel lines of varying width; each line comprising a single continuous segment in which the width varies based on the density of the gray level required to form the gray level image; and transferring the set of lines to a pattern of conductor/insulator lines on a substrate.

Method for forming graphical images in semiconductor devices

A method to statically balance Silicon-On-Insulator (SOI) parasitic effects is disclosed. Additionally, eight device Static Random Access Memory (SRAM) cells using the method are provided. A balanced output stage that creates a particular set of parasitic effects, as seen by a node connected to the output of the balanced output stage, is provided. If the balanced output stages are used at both outputs of a SRAM cell, the nodes to which the outputs of the balanced output stages are connected will see the same parasitic effects when the transistors in the balanced output stages are off. Thus, the balanced output stages can create the same effect on both the true and complement bitlines of an SOI SRAM, thereby balancing both of these lines and improving access times.

Method to statically balance SOI parasitic effects, and eight device SRAM cells using same

The method for selecting hierarchical interaction in a hierarchical shapes processor increases the operator's access and control over the handling of the design's hierarchical structure. The shapes of each cell are considered in accordance with a specified hierarchical relationship having constraints defined by the chosen mode of shape processing. The hierarchical relationships provide additional shape processing modes depending on the operator's physical design requirements.

Method for selecting hierarchical interactions in a hierarchical shapes processor

A wiring design tool which detects minimum area vias and replaces them with redundant vias pairs. The invention uses the definitions for single vias and tracks in a grid coordinate system and a file describing the design wires and their interconnections to select the most favorable direction for the placement. The invention accomplishes this by examining the directions one track away from each single via at various levels and according to the methodology of this invention, detects a possible situs for a redundant via pair, preferably where a segment of wire on the same net already exists. If no design rule violation occurs the system replaces the single via with a redundant via pair.

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Mansfield, PA, United States of America

William F Pokorny