Harris Corporation

William F Johnstone

William R Young

David H Damerow

A decimating memory includes a memory having addressable memory locations. The memory forms a plurality of registers, each of the registers including at least one addressable memory location. The plurality of registers form a forward shifting data section and a reverse shifting data section. A first decoder operates the registers in the forward shifting data section and all but a first of the registers in the reverse shifting data section as FIFO registers via read and write addressing of the addressable memory locations to input and output data samples. The read and write addressing of the addressable memory locations is offset with respect to one another to provide a decimation factor. A paintbrush decoder operates the first register in the reverse shifting data section as a LIFO register for reverse sequencing data samples within blocks of data samples received from the forward shifting data section. Each of the registers in the forward shifting and reverse shifting data sections provide an output. An ALU section operates on the outputs and provides a decimating memory output.

Decimating filter

Decimation circuitry having a forward shifting data section receiving data samples in order including a plurality of forward decimation registers coupled in-line and providing a forward register output. Each forward decimation register operates as a first-in-first-out (FIFO) register having a decimation depth. A backward shifting data section includes a plurality of backward decimation registers having a decimation depth coupled in-line and providing a backward register output. One of the backward decimation registers which receives data samples in sequence from one of the forward decimation registers can function as both a last-in-first-out (LIFO) and a FIFO register, when a LIFO register, it operates to reverse blocks of data samples wherein the size of each block corresponds to the decimation rate. Each reversed block is then shifted through the backward shifting data section. Each of the other backward decimation registers operates as FIFO register. The decimation circuitry can be used to form a digital filter cascadable into various sizes.

Fold and decimate filter architecture

A decimating memory includes a memory having addressable memory locations. The memory forms a plurality of registers, each of the registers including at least one addressable memory location. The plurality of registers form a forward shifting data section and a reverse shifting data section. A first decoder operates the registers in the forward shifting data section and all but a first of the registers in the reverse shifting data section as first in first out registers via read and write addressing of the addressable memory locations to input and output data samples. The read and write addressing of the addressable memory locations is offset with respect to one another to provide a decimation factor. A paintbrush decoder operates the first register in the reverse shifting data section as a last in first out register for reverse sequencing data samples within blocks of data samples received from the forward shifting data section. Each of the registers in the forward shifting and reverse shifting data sections provide an output. An arithmetic logic unit section operates on the outputs and provides a decimating memory output.

Decimation circuit employing multiple memory data shifting section and

Each cross-point includes a first and second storage device with the next cycle information being stored in the first storage device and transferred to the second storage device which has the present cycle information. The output of the second storage means is used in combination with a second controlling input to control the switch or logic at a cross-point. In one embodiment, the cross-point state is stored in the storage devices and is combined with the input data to provide an output on the data output line. In another embodiment, input data is stored in the storage devices and is combined with input state selects to provide an output on the data output line.

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Palm Bay, FL, United States of America

William F Johnstone