Harris Corporation

William F Hartman

Robert W Boyd

Luther L Crabtree

William P Osborne

A modified Fano signal processing scheme for a sequential codec defers a portion of path metric processing operations to a subsequent processing cycle by parallel branch metric processing. Rather than calculate and execute the effective path metric threshold changes in the same processing cycle, any threshold change that should result from the present processing cycle is fed forward to the branch metric calculation circuit so as to be readily available for use in the next processing cycle without having to be stored and subsequentially processed during the same processing cycle. The error correction/data recovery processor preferably employs a syndrome generator configured of a programmable read only memory which receives the bit stream to be processed and supplies impulse response bits to respective stages of a bidirectional shift register/exclusive-OR circuit. Also, the error correction processor is configured to accommodate multiple code rates through a common hardware arrangement which is implemented on the basis of a rate 3/4 code that makes it readily adaptable to both rate 1/2 and 7/8 codes.

Error correction processing scheme for sequential codec

In a spread-spectrum receiver, a predetermined noise floor voltage, supplied together with the output of the correlation detector as a control voltage for an AGC amplifier, is subjected to a pre-signal reception adjustment or calibration, in order to compensate for drift in the noise floor or reference voltage and to correct for gain errors in the correlation detector channel thereby insuring proper operation of the detector during the sequential detection process. For this purpose, a prescribed random signal sequence, totally different from that contained in any useful transmission to be acquired, is initially applied to the correlation detector for a predetermined period of time or calibration interval. The output of the correlation detector is sampled and stored, successive samples are compared with the predetermined or fixed reference noise floor voltage, and successive adjusted noise floor reference values are produced, representative of differences between the noise level in successive correlation samples and the predetermined noise reference. These adjusted reference values are accumulated and this accumulated noise floor is fed back to the AGC amplifier as the noise floor control reference. At the end of the calibration interval, the receiver is switched to a normal operating mode and control of the AGC amplifier is determined by the noise floor reference level which has been adjusted or calibrated to the voltage represented by the accumulated noise floor level at the end of the calibration interval. Preferably, the calibration circuitry is implemented in digital form, with the duration of the calibration interval being controlled by a digital counter which counts clock pulses up to a prescribed number and then prevents further accumulations of noise reference values. The output of the counter may also be coupled as a control signal to cause a spread-spectrum signal acquisition PN sequence to be substituted for the random noise sequence which had been applied to the correlation detector during the calibration mode.

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Palm Bay, FL, United States of America

William F Hartman