Raynet Corporation

Other

Ericsson Gmbh

Ericcson Inc.

William F Ellersick

William L Geller

Steven P Saneski

David M Arstein

Paulmer M Soderberg

Rocco Falcomato

A digital phase acquisition clock recovery circuit includes a digital phase-locked loop that employs a truth table decoder to set the actual delay through a plurality of individual delay elements to generate a plurality of clock phase signals approximately equally spaced in time over one reference clock cycle, and a data sampler circuit that generates a plurality of received data samples from an incoming data sample taken at the rising edge of the respective clock phase signals and synchronizes the data samples to reference clock on a bit period-by-bit period basis. A digital phase acquisition circuit includes an edge detector which evaluates the data samples over each bit period to detect the location of a transition between respective adjacent samples, wherein logic is employed to continually determine the 'relative quality' of each data sample, based upon its sampling time being furthest from a detected edge transition. The data sample phase associated with the highest relative quality value integrated over time is then used to recover the incoming (i.e., optimally phased) data signal.

Digital phase acquisition with delay locked loop

A combined signalling and PCM cross-connect and packet assembly/disassembly engine includes a cross-connect memory, wherein the memory advantageously includes both a subscriber PCM channel memory that cross-connects bus side PCM channels to optical fiber timeslots, and a separate signalling memory that cross-connects associated signalling data channels to optical fiber timeslots. In particular, the PCM and signalling data memories are substantially the same size and each signalling data channel is mapped to an address in the signalling memory that corresponds to the PCM memory address of the associated PCM channel. Cross-connect information used for the PCM channels is also used to cross-connect the associated signalling channels. Cross-connect and packet engine functions are combined, thereby eliminating the need for a separate buffer to accommodate differences in transmission rates between them. A single control store with an associated fiber timeslot counter is also connected to the packet engine circuit, which supports both PCM and signalling data channels.

Combined signalling and PCM cross-connect and packet engine

A dc-coupled receiver for a shared optical system includes an input feedback amplifier circuit which establishes a dc reference baseline voltage level for incoming packets of data. A pair of sample-and-hold circuits are connected in parallel to receive and sample signals from the feedback amplifier circuit when no data is being transmitted and at the initial edge of incoming packets of data. A voltage divider circuit receiving signals from the sample-and-hold circuits establishes a dc slicing level for each incoming packet of data. An output feedback circuit can be added to compensate for offset error without affecting the performance of the sample-and-hold circuitry.

DC-coupled receiver for shared optical system

An office interface unit (OIU) transfers data and signaling between a telephone local exchange and distribution lines. Information from the telephone local exchange is contained in repetitive frames containing signaling time slots which each contain two distinct nibbles of information. The OIU translates each local exchange signaling channel into first and second internal signaling channels, each internal signaling channel containing information representative of one signaling nibble therein. This simplifies DSO time slot interchange in the OIU. In addition, each internal signaling channel is provided with at least one additional significant signaling bit thereby providing additional signaling states so that the OIU equipment can account for multiple types of telephone local exchange equipment easily. Furthermore, each internal signaling channel is also provided with at least one data coding check bit thereby providing an easy and efficient method of determining whether or not bit errors are occurring in the OIU or equipment connected thereto.

Method and apparatus for translating signaling information

An inrush current limiting circuit in accordance with the principles of the present invention limits initial current flow to a highly initially reactive power load. The current limiting circuit comprises a plug in connection to a power source and two conductor paths leading from the plug in connection. A power FET has a source element to drain element path in series with one of the conductor paths and has a gate connection. A bipolar transistor is connected to shunt the gate element of the power FET to the potential at its source element when the bipolar transistor is conducting, thereby to limit the current passing through the power FET. A sense resistor is in series with one of the conductor paths for controlling a base element of the bipolar transistor to cause it to conduct when current through the sense resistor exceeds a predetermined amount. The bias resistor is connected to the gate element of the power FET normally to bias it into full conduction between the source and drain elements when the bipolar transistor is not conducting.

Growing community of inventors

Redwood City, CA, United States of America

William F Ellersick