Digital Equipment Corporation

William F Bruckert

Thomas D Bissett

John Munzer

David E Kovalcin

Dennis Mazur

Alfred J Dellicicchi

Glenn A Dearth

John C Manton

James Melvin

Mitchell O Norcross

Barbara H Altman

Tryggve Fossum

Barry J Flahive

Thomas B Hawkins

Ajai Thirumalai

Norbert H Riegelhaupt

Allan E Helenius

Richard E Glackemeyer

Kenneth A Ward

Frank Bernaby

Jay H Bhatia

Jay Amirmokri

Peter R Mott, Jr

Paul Paternoster

Ann Katan

John A DeRosa, Jr

Carlos Alonso

Ravi Nene

James V Lacy

According to one aspect of the invention, an apparatus includes a first processor coupled to a first system bus to provide data to a cache and a memory, and a second processor coupled to the first system bus and a second abbreviated system bus to receive read data from said first system bus. In accordance with a further aspect of the invention, an apparatus includes means for correcting errors in memory. In accordance with a further aspect of the invention, an apparatus includes a number of computing systems each including a memory device mounted on an infrequently replaced hardware unit, and capable of communicating with the number of computing systems. In accordance with another aspect of the invention, an apparatus includes a counter, means for detecting a selected state of said counter, and means, responsive to output signals from said counter, for selectively permitting or inhibitting transfer of data fed to a recirculating state device. In accordance with a further aspect of the invention, an apparatus includes a first means for providing a first clocking signal, a second means for providing a second clocking signal, means for providing an error signal responsive to an offset between edges of the first and second clocking signals.

Apparatus and method of data transfer between systems using different

Method and apparatus for reducing checking costs in fault tolerant

The software error handling determines the nature of the fault and takes different action depending upon the nature of the fault. If the fault prevents the data processing system from continued reliable operation, then the element causing the fault is immediately disabled. Otherwise, the element which is the source of the fault is treated so that it does no harm to the system and causes no further faults. The element can then be completely handled during normal software status checks.

Method of handling errors in software

A dual processor computer system includes a first processing system having a central processing unit which executes a series of data processing instructions, a data bus system for transferring data to and from the first central processing unit, a memory unit coupled to the first central processing unit, and a cross-link communications element for transferring data into and out of the first processing system. A similarly configured second processing system, operating independently of the first processing system, is also provided. The cross-link communications element associated with the second processing system is coupled to the cross-link communication element of the first processing system, for transferring data into the second processing system from the first processing system and for transferring data into the first processing system from the second computer system.

Fault tolerant, synchronized twin computer system with error checking of

Resets on a data processing system are targeted to specific locations of that processing system and have different effects. Some resets are transparent to instruction execution while other resets will interrupt the normal execution of instructions. In addition, in a multi-zone environment resets in one zone do not automatically propagate to the other zone; instead, each zone generates its own resets.

Targeted resets in a data processor including a trace memory to store

A dual processor data processing system having interprocessor error checking includes a first central processing unit executing a series of instructions. A second central processing unit executes the same series of instructions independently of and in synchronism with the first central processing unit. A first data bus is coupled to the first central processing unit for receiving data to be input to the first central processing unit and a second data bus is coupled to the second central processing unit for receiving data to be input to the second central processing unit. Error checking devices are coupled to the first and second data busses for checking data transmitted over the first and second data busses and for detecting errors on I/O reads prior to delivery of the data to the first and second central processing units. The error checking devices include comparison means for indicating an error when the data on the first and second data busses are unequal. Error isolation devices are responsive to an error detected from the error checking means for analyzing the cause of error while maintaining system synchronization.

Dual rail processors with error checking on I/O reads

A process for transferring data via DMA between a system resource and a controller via switching logic. During a setup write transaction, the switching logic is set up to enable DMA data to be transferred between a particular system memory and a selected system resource. The setup write transaction also is used to initialize the DMA byte counter. During a subsequent write transaction, DMA pointer registers are initialized with appropriate starting addresses. The controller then transmits a DMA start code and the system resource responds by transmitting an acknowledge code. At that time, DMA data is transmitted between the controller and the system resource via the switching logic.

Protocol for transfer of DMA data

Hardware error processing is undertaken to analyze the source of the error and to preserve sufficient information to allow later software error processing. The hardware error processing also allows, for certain errors, complete recovery without interruption of the sequence of instruction execution.

A fault tolerant computer system has a central processing system which includes at least one set of data pathways, and executes a series of data processing instructions including the transfer of messages along the plurality of data pathways. At least one set of transaction data storage devices are coupled to the data pathways for storing a predetermined number of successive messages transferred most recently on the data pathways. Error checking devices are included for detecting the presence of errors in the central processing system. Error storage devices are coupled to the transaction data storage devices and the error checking devices for causing the transaction data storage devices to cease storing additional messages in response to the detection of errors by the error checking device.

Fault tolerant computer systems with fault isolation and repair

Method and apparatus for testing the operation of modules for use in a fault tolerant computing system that consists of two distinct computing zones. Diagnostic testing is performed when the system is powered on, the modules being subjected to module, zone and, if both zones are available, system diagnostic tests. Indications of faults detected during diagnostic testing are stored in an EEPROM on each module. Such fault indications can be cleared in the field by correcting the fault condition and successfully rerunning the diagnostic test during which the fault was detected. Indications of operating system detected faults are also stored in each module EEPROM. However, such fault indications are not field clearable.

Apparatus and method for documenting faults in computing modules

Method and apparatus for controlling initiating of bootstrap loading in a computer system having first and second discrete computing zones is disclosed. Each computing zone includes a status register for storing an operating system run (OSR) bit indicating that the zone has initiated bootstrap loading. A cable connects the computing zones to allow the first and second zones to read the status registers in the second and first zones, respectively. A CPU in each zone only enables initiation of bootstrap loading if the OSR bit in the other zone is not set.

Method and apparatus for controlling initiation of bootstrap loading of

In a processing system having duplicate sets of elements, often called rails, to move rail unique data from one set of elements to the other set of elements, the unique data is moved to a scratchpad memory and then copied into a common memory after certain error checking is disabled.

Method of converting unique data to system data

A data handling system for transferring data between two units, the data being transferred in blocks of a selected number of data words, up to predetermined maximum number. A buffer stores the data being transferred. The buffer includes a plurality of stages arranged serially from an input end to an output end, the number of stages being equal in number to the predetermined maximum number of data words that may be transferred in a block. If the number of data words being transferred is less than the predetermined maximum number, as indicated by a control signal from the unit transmitting the data, the buffer either receives the data in the stage a number of stages from the output end, or transmits the data from the stage a number of stages from the input end, equal to the number of words being transferred in the block.

Adjustable buffer for data communications in a data processing system

A fault tolerant computer system having a first processing system which includes a first data processor for executing a series of data processing instructions. A first data output terminal outputs data from the first processing system. A second processing system, substantially identical to the first processing system, operates independently from the first processing system. The second processing system includes a second data processor for executing the series of data processing instructions in the same sequence as the first data processor. It also includes a second data output terminal for outputting data from the second processing system. A synchronizing device is coupled to the first and second data processors for maintaining the execution of the series of data processing instructions by the first and second processing systems in synchronism. Fault detection devices are coupled to the first and second data output terminals for comparing the data output from the first processing system with the data output from the second processing system. The fault detection devices identify the presence of an error when the data output from the first processing system at the first output terminal is different from the data output from the second processing system at the second output terminal.

Dual zone, fault tolerant computer system with error checking in I/O

A fault tolerant computer system includes a fault tolerant data processing module which has means for detecting and correcting errors in the operation of the data processing module to maintain a high degree of data integrity. Data transmission control devices control the transmission of all data to the fault tolerant data processing module and the receipt of all data into the fault tolerant data processing module. Input/output terminals are coupled to the data transmission control means for receiving and transmitting data. A non-fault tolerant input/output module is coupled to transmit the data to the input/output terminals of the fault tolerant data processing module. This module includes a read device for transferring data to the fault tolerant computing system in response to requests from the data transmission control devices, and a firewall for preventing the non-fault tolerant input/output module from initiating transfers of data to the fault tolerant data processing module.

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Northboro, MA, United States of America

William F Bruckert