Digital Equipment Corporation

University of Washington

Emulex Design & Manufacturing Corporation

Emulex Corporation

Equator Technologies, Inc.

Emulex Coproration

William Eugene Morgan

Bruce Gregory Warren

Carl Joseph Mies

William Patrick Goodwin

Chandramohan Amyangot Thekkath

Henry M Levy

Daniel S Cobb

Anna R Karlin

Michael J Feeley

Gerald S Bell

Alec Carlson

A device, integrated circuit and method for generating simulated errors are disclosed. In the disclosed device, integrated circuit and method, an original data value is read from a memory. The original data value is intercepted by the integrated circuit. The integrated circuit is operable to virtualize an error in the original data value to generate a modified data value. The integrated circuit is also operable to generate an interrupt according to the virtualization. This disclosure may be particularly useful for high-level memory validation.

Generation of simulated errors for high-level system validation

Embodiments of the invention enable error simulation for system validation. Errors can be simulated by modifying data presented to the processor as well as generating interrupts consistent with the modified data in the ASIC hardware. Modify logic may be added to the ASIC so when the microprocessor attempts to read a specific address, the modify logic may mask one or more of the data bits returned by the requested address. Address, bit mask, and force value data may be stored in registers to determine which address may be modified, the bit location to be modified, and the value that bit location should be changed to. Selection logic may then determine whether data from the modify logic or the unmodified value from an attached device should be sent to the ASIC interface and on to the microprocessor. A timer may also be used to decouple the setup from the test.

This invention relates to error simulation for system validation. Errors can be simulated by modifying data presented to the processor as well as generating interrupts consistent with the modified data in the ASIC hardware. Modify logic may be added to the ASIC so when the microprocessor attempts to read a specific address, the modify logic may mask one or more of the data bits returned by the requested address. Address, bit mask, and force value data may be stored in registers to determine which address may be modified, the bit location to be modified, and the value that bit location should be changed to. Selection logic may then determine whether data from the modify logic or the unmodified value from an attached device should be sent to the ASIC interface and on to the microprocessor. A timer may also be used to decouple the setup from the test.

A method for managing tasks in a data processing system having a shared task, which may be performed in hardware, software, or a combination of both. In response to a request from a requesting task, the task manager of the data processing system initiates performance of the shared task on behalf of the requesting task. At selected points in the performance of the shared task, the requesting task may cooperate with the shared task to selectively store watchpoints, each comprising sufficient information about the then-current status of the shared task to allow resumption of that task. During the performance of the shared task, the requesting task can determine if the shared task is still performing that task on behalf of the requesting task. If the requesting task determines that the task manager has interrupted the performance of the shared task on behalf of the requesting task prior to completion thereof, the requesting task may thereafter request the task manager to reinitiate performance of the shared task at the most recently stored watchpoint.

Method for managing shared tasks in a multi-tasking data processing system

A system and method for managing memory in a network. In a computer network in which multiple computers (nodes) are interconnected by a network, the primary memory on one node may be used to store memory data (pages)from other nodes. The transfer of a data page over the network from the memory of a node holding it to the memory of another node requesting that data gives improved performance when compared to the transfer of the same data from disk, either local or remote, to the requesting node. Global information about the disposition of the nodes and their memories in the network is used to determine the nodes in the network that should best be used to hold data pages for other nodes at a particular time. This information is exchanged by the nodes periodically under command of a coordinating node. The system includes distributed data structures that permit one node to locate data pages stored in another node's memory, procedures to determine when global information should be recomputed and redistributed, and procedures to avoid overburdening nodes with remote page traffic.

Using global memory information to manage memory in a computer network

A local area print server for connection to a printer to form a printing system for servicing printing requests is disclosed. The local area print server both controls the servicing of printing requests by the printer, and in response to printer requests for resources needed to satisfy a printing request, either provides required resources, or obtains the resources from a remote component. A resource manager is provided for receiving resource requests from the printer for resources required to satisfy particular printing requests, and, in response to receiving such requests, forwards the necessary resources to the printer. There is also a status collector adapted for receiving status block messages internally generated by the printing system containing information regarding the changing state of the system and in response to receiving the messages retransmit same to one or more of the other local area print server internal modules that respond to specific printing system status changes.

Growing community of inventors

Seattle, WA, United States of America

William Eugene Morgan