Cisco Technology, Inc.

William Eklow

Hongshin Jun

Gyaneshwar S Saharia

Sun-Gyu Kim

A method to perform component testing by supplying test patterns to a serial input pin coupled to an IEEE 1149.6 boundary-scan cell that is associated with an IEEE 1149.6 test receiver. The test receiver is configured to operate in a scan test mode. The output from the test receiver circuit is coupled to a logic block to be scan tested. The output from the logic block is coupled to a serial output pin on the integrated circuit during scan test mode. High performance integrated circuits can use SerDes pins in a scan test mode to be scan tested without impacting mission critical signals.

Removing scan channel limitation on semiconductor devices

Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, mechanisms, and means for providing a JTAG to system bus interface for accessing embedded analysis system(s). JTAG commands are received and converted into commands sent out a bus to a device including an embedded analysis instrument, with results received over the bus forwarded out the JTAG interface to an external device. Such a JTAG to system bus interface may eliminate the need to provide separate JTAG TAP interfaces on each ASIC of a board, and/or eliminate the need to daisy chain multiple TAP interfaces of multiple ASICs in order to provide a single TAP interface for accessing the multiple embedded testing instruments.

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San Jose, CA, United States of America

William Eklow