International Business Machines Corporation

Tessera Intellectual Properties, Inc.

William Edward Sablinski

Mario John Interrante

Raymond A Jackson

Sudipta Kumar Ray

Peter Jeffrey Brofman

Mark G Courtney

Hilton T Toy

Lewis Sigmund Goldmann

Kathleen Ann Stalter

Frank Louis Pompeo

Subhash Laxman Shinde

Shaji Farooq

Sarah Huffsmith Knickerbocker

Kamalesh K Srivastava

Tien-Jen Cheng

Patrick Anthony Coico

Jonathan H Griffith

Raj N Master

Jeffrey Thomas Coffin

David E Eichstadt

Li Ming Wang

Kathleen Ann Lidestri

Julie C Biggs

Michael J Ellsworth, Jr

Mukta G Farooq

David L Edwards

Roger Allan Quon

Sushumna Iruvanti

Thomas Anthony Wassick

Thomas Edward Lombardi

Raed A Sherif

Brenda Lee Peterson

Karl J Puttlitz, Sr

Gregory Blair Martin

Armando S Cammarano

Joseph M Harvilchuck

Balaram Ghosal

Stephen S Drofitz, Jr

Edward F Handford

Michael A Gaynes

Jeffrey Allen Zitz

How Tzu Lin

Steven Paul Ostrander

David James Alcoe

Randall Joseph Stutzman

Amit Kumar Sarkhel

David C Linnell

Charles L Reynolds

Harvey Charles Hamel

Steven E Molis

Renee L Weisman

Jiali Wu

L Wynn Herron

Megan J Shannon

Roger A Quinn

Christopher Todd Spring

A method to reduce liquid polymer macromolecule mobility through forming a polymer blend system is provided. More particularly, a small amount of polymer crosslinker is added to a liquid polymer matrix to prevent intermolecular movement. The crosslinker functions as cages to block linear or branched linear macromolecules and prevent them from sliding into each other.

Method to improve wettability by reducing liquid polymer macromolecule mobility through forming polymer blend system

A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening of a first diameter, and a solder material is formed over the barrier layer using a second patterned opening of a second diameter. The second patterned opening is configured such that the second diameter is larger than the first diameter.

Forming robust solder interconnect structures by reducing effects of seed layer underetching

A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.

Method for forming robust solder interconnect structures by reducing effects of seed layer underetching

A lead free solder hierarchy for use in the second level solder connection of electronic components such as joining an electronic module to a circuit board. An off-eutectic solder concentration of SnCu or SnAg is used for the module side connection. This off-eutectic solder contains sufficient intermetallics to provide the module side connection with a robust second level assembly and rework process. The off-eutectic composition provides an inter-metallic phase structure in the module side fillet during assembly. The inter-metallic phase structure eliminates problems of tilt and collapse during second level assembly and aids in rework by providing a more cohesive joint allowing removal of the columns from the board without simultaneous removal from the module.

Solder hierarchy for lead free solder joint

An electronic package having a solder interconnect liquidus temperature hierarchy to limit the extent of the melting of the C4 solder interconnect during subsequent second level join/assembly and rework operations. The solder hierarchy employs the use of off-eutectic solder alloys of Sn/Ag and Sn/Cu with a higher liquidus temperature for the C4 first level solder interconnections, and a lower liquidus temperature alloy for the second level interconnections. When the second level chip carrier to PCB join/assembly operations occur, the chip to chip carrier C4 interconnections do not melt completely. They continue to have a certain fraction of solids, and a lower fraction of liquids, than a fully molten alloy. This provides reduced expansion of the solder join and consequently lower stresses on the C4 interconnect.

Structure and method for lead free solder electronic package interconnections

An optical-electronic package for an electronic device provides electrical connections to the electronic device and optical fiber connections to the electronic device. The package includes a high thermal conductivity base which has a pedestal to support and provide heat transfer connection to the electronic device. A seal band is formed on the base and a casing is bonded to the seal band. The casing has side feedthroughs for the electrical connections from the electronic device, and the casing has top feedthroughs or grooves for the optical fiber connections from the electronic device. A lid is hermetically sealed to the top of the casing. The lid has retractable means for forming a bend in the optical fibers to provide strain relief when the lid is placed on the casing. The retractable means for forming a bend in the optical fibers is retractable once the lid is sealed on the casing.

Optoelectronic package structure and process for planar passive optical and optoelectronic devices

Electronic packages incorporating EMI shielding, and particularly semiconductor devices which incorporate semiconductor chip-carrier structures having grounded bands embedded therein which are adapted to reduce outgoing and incident EMI emissions for high-speed switching electronic packages.

EMI shielding for semiconductor chip carriers

Interconnection process for module assembly and rework

A temporary attach article of a first component to a second component which includes a first component having a first volume of a fusible material; a second component having a second volume of fusible material; and the first and second components being joined together through the first and second volumes of fusible material, wherein the first volume of fusible material has a melting point higher than a melting point of the second volume of fusible material so that the first and second components may be joined together without melting of the first volume of fusible material and wherein the second volume of fusible material is 5 to 20% of the first volume of fusible material. Also disclosed is a method for temporary attach of devices to an electronic substrate.

Temporary attach article and method for temporary attach of devices to a substrate

The present invention relates generally to a new semiconductor chip carrier connections, where the chip carrier and the second level assembly are made by a surface mount technology. More particularly, the invention encompasses surface mount technologies, such as, Ball Grid Array (BGA), Column Grid Array (CGA), to name a few, where the surface mount technology comprises essentially of a non-solder metallic connection, such as, a copper connection. The present invention is also related to Column Grid Array structures and process thereof.

High density column grid array connections and method thereof

This invention relates to a solder structure which provides enhanced fatigue life properties when used to bond substrates particularly at the second level such as BGA and CGA interconnections. The solder structure is preferably a sphere or column and has a metal layer wettable by solder and the structure is used to make solder connections in electronic components such as joining an electronic module such as a chip connected to a MLC which module is connected to a circuit board. The solder structure preferably has an overcoat of solder on the metal layer to provide a passivation coating to the metal layer to keep it clean from oxidation and corrosion and also provide a wettable surface for attachment of the solder structure to solder on the pads of the substrate being bonded.

Method for enhancing fatigue life of ball grid arrays

A solder preform is provided for forming interconnections between multilayer ceramic substrates comprising an upper layer and lower layer of solder separated by an intermediate layer of a material which is wettable by solder and which does not melt at the temperatures used to reflow the solder and form the connections. The solder preform is used to join the substrates and is particularly useful to simultaneously electrically interconnect the substrates and to form a hermetic seal between the substrates being joined.

Solder disc connection

Growing community of inventors

Beacon, NY, United States of America

William Edward Sablinski