Alcatel Network Systems, Inc.

Corning Glass Works

Alcatel

Alcatel Na, Inc.,

William E Powell

William B Weeber

Richard W Peters

William H Stephenson, Jr

Manal E Afify

Klaus-Hartwig Rieder

Gunter Horsch

Richard Marion Czerwiec

Joseph E Sutherland

Timothy J Williams

Joseph Lee Smith

Michael J Gingell

Claude M Hurlocker

Ertugrul Baydar

Dale L Krisher

Raymond E Tyrrell

Donald P Brezinski

William J Fox

Gus C Sanders, Jr

Richard J Sanders, Jr

Stephen C Dunning

Hal A Thorne

Francis G Noser

Richard G Magner

Jak Yaemsiri

Keith L Bernhardt

Jeffrey P Jones

Dana Merrill

Wenkwei Rou

Camille A Abu-Saba

Michael Sutton

Georges A Roger

David T Hayes

O Lamar Bishop

M Rodney Briscoe

Kenneth J Stoia

V Paul Runyon

Heinrich T Sonnenberg

Patrick M Farrell

Victor W Wilkerson

Mohammad S Arani

052440872 An existing synchronous residual time stamp (SRTS) algorithm (76, 78, 80, 82, 106, 104) is used in conjunction with adaptively filtered buffer fill information (74) to reconstruct an original constant bit rate (CBR) payload clock rate (102) for asynchronous transfer mode (ATM) CBR payloads (88, 96). The SRTS time stamp (96) is used as the primary factor used to recover the payload clock rate, but a secondary payload frequency correction factor (112) is generated by filtering (118, 120) the desynchronizer buffer fill position. This correction factor is determined as part of a feedback arrangement which adaptively (128) alters the filtering time constant based on the offset position of the buffer from its center. In this way, payload clock frequency (102) is corrected, even in the presence of loss of synchronization PRS traceability between mapping and desynchronizer nodes to keep the desynchronizer buffer from overflowing.

Low jitter timing recovery technique and device for asynchronous

Digital signal processing techniques are used to synthesize a range of output frequencies locked to a non-pullable reference oscillator, and the synthesized output frequency is used in a slave low bandwidth phase-locked loop; by increasing digital resolution in a phase accumulation register, any desired resolution of output frequencies can be generated. The range of output frequencies is synthesized in such a way as to generate only high-frequency jitter, which can be easily filtered by follow-on, low-cost, relatively high bandwidth phase-locked loops which are typically needed for frequency multiplication in a given system. The magnitude of residual jitter is easily controlled by proper choice of the non-pullable oscillator reference frequency, the output frequency range to be synthesized and various other digital factors, such as divider ratios. Improved noise performance is achieved while still maintaining a wide pulling range of the composite phase-locked loop.

Synchronized clock using a non-pullable reference oscillator

A method and an apparatus are provided to achieve fast phase settling when a reference signal for a phase locked loop changes from a first frequency to a second frequency, such as during holdover recovery in a synchronous optical network. The present method acquires the second frequency with a phase locked loop (24). After the frequency is acquired, the integral register (39) of the phase locked loop (24) is loaded with the contents of the output frequency register (34) of the phase locked loop (24). The phase detector (28) of the phase locked loop (24) is then realigned to the reference signal.

Method and apparatus for achieving fast phase settling in a phase locked

A desynchronizer (20) for desynchronizing data stored within synchronous payload envelopes of a synchronous communication protocol such as SONET (Synchronous Optical Network), provides for smoothing the periodically discontinuous clock signal associated with that data after the synchronous communication protocol overhead has been removed. The desynchronizer accommodates for shifts in the position of the payload envelope and hence, the data within the synchronous communication frame as well as adjustments within the data itself due to asynchronous bit stuff information. The desynchronizer utilizes a leak filter (26) having a linear branch (54) and an integrator branch (56), both branches having adjustable factors (61, 63, 65, 88, 90, 91, 93, 95, 100, 102, 105) regarding their operation, wherein the adjustable factors are selected depending upon threshold values (86, 87, 89, 62) which in turn are based upon the difference between the average write address and read address for the associated elastic store (22) within which the incoming data removed from the synchronous communication system frame is temporarily stored. The leak filter (26) forms part of a phase locked loop which in turn adjusts the read clock frequency (46) in a manner which minimizes overflow or underflow of the elastic store while simultaneously minimizing the rate of change of the read clock rate so as to limit jitter. A fault recovery apparatus forms part of the desynchronizer for enabling fastlock high gain factors (67, 97, 107) to quickly adjust the read clock when elastic store overflow or underflow occurs. The gain factors associated with both the linear branch and integrator branch are provisionable (118, 120) as well as elastic store size and thresholds resulting in a desynchronizer which can be modified to meet the particular jitter requirements of a particular synchronous communication system. A calculation engine (82) performs iterative calculations to generate the leak filter output value using a reduced number of logic gates for ASIC implementation.

Calculation apparatus for performing algebraic and logic computations

A desynchronizer for processing pointer movements and stuff bit information associated with payload data transmitted within a synchronous digital communication network. The desynchronizer includes a payload extractor (58) for removing payload data and storing it in an elastic store (32). The extractor also removes the pointer and stuff bit information which is passed through a digital low pass bit leaking module (36). The difference between the write and read addresses of the elastic store is determined (modules 48 and 50) and algebraically combined with the output of the bit leaking module (36) so as to provide the necessary data for adjusting the instantaneous frequency of a variable controlled oscillator (44) that generates the timing base for the read clock for reading the payload from the elastic store in a manner that minimizes jitter.

Desynchronizer for adjusting the read data rate of payload data received

Incremental phase smoothing desynchronizer and calculation apparatus

The circuit arrangement of the invention presents an oscillator, whose frequency can be linearly varied within a wide control range, without affecting the oscillator's stability. The frequency of a fixed frequency generator (1) is divided to the desired frequency by a frequency divider (2), whose divider ratio can be varied in very small steps, and the resulting jitter is filtered out by a very simple phase control circuit (3). Improved short-term stability and holdover performance are also achieved. The oscillator can be universally used as clock generator in all digital circuit arrangements.

Digitally controlled fractional frequency synthesizer

A synchronous optical transmission system for interfacing SONET formatted channels to lower speed channels in either a SONET format or otherwise. The transmission system incorporates a fiber transmission system, terminal multiplexers and add/drop multiplexers that in turn incorporate a plurality of features, such as parallel scrambling circuitry, frame synchronization circuitry and the like.

Synchronous optical transmission system

A parallel frame synchronization circuit converts an incoming serial bit stream containing frame synchronization information into parallel data words on arbitrary boundaries of fixed bit length. Detectors forming part of the present invention determine from the parallel converted data the presence of synchronization information so as to align the incoming serial data into parallel data aligned on frame boundaries by manipulating parallel words. The present invention is particularly suited for fabrication in complimentary metal oxide silicon (CMOS) technology and in a preferred embodiment is used to synchronize incoming data comporting to the synchronous optical network (SONET) telecommunication standard.

Parallel bit detection circuit for detecting frame synchronization

A parallel pseudo-random generator emulates a serial pseudo-random generator which in turn is defined by a polynomial of the type 1+x.sup.M + . . . +x.sup.P ; that is, wherein the serial outputs are generated such that the next serial output value is based upon an Exclusive OR combination of at least two preceding serial output values. The parallel pseudo-random generator comprises latches and Exclusive OR gates, the number of latches and Exclusive OR gates each being at least equal to the polynomial order of the serial pseudo-random generator defining polynomial. The outputs of the latches represent the outputs of the parallel pseudo-random generator and may be used to scramble data on parallel data lines. A method is disclosed for determining the interconnects between the latch outputs and the Exclusive OR gate inputs based upon the number of latches and the serial pseudo-random generator defining polynomial.

Parallel pseudo-random generator for emulating a serial pseudo-random

By providing two comparators, each of which have a reference voltage level source connected to one input, and separate voltage level producing/enhancing circuits connected to the contacts of a relay, so that each alternate switch configuration produces a different voltage level at the two comparators, a unique relay switch detection circuit is attained. Preferably, three separate voltage level producing/enhancing circuits are employed, with one circuit connected between the relay output and the two comparators, while the other two circuits are connected to the primary or the secondary relay contacts. Futhermore, the voltage level resulting from each particular switch configuration is pre-set relative to the reference voltage level source imputs to assure that the two comparators produce different combined outputs for each alternate switched condition.

Contact status detector

An analyzer for electrophoretic samples includes a sensor of extremities, more particularly valleys, in the output from the detector. The analysis of electrophoretic samples includes integration of the area under each of the fractions of the multicomponent output. In order to integrate each of the components, it is necessary to detect valleys in the output. The detector output is first applied to a non-linear processor such as a logarithmic amplifier and a differentiator. The logarithmic amplifier changes the shape of the output to make the detection less dependent upon relative component amplitude. A threshold comparator produces a pulse when the slope of the analyzer output, as represented by the output of the differentiator, exceeds a threshold. The threshold is changed after the detection of the first valley. Noise suppression circuitry prevents the detector from responding to closely occurring extremities in the analyzer output.

Valley sensor for an electrophoretic analyzer

An analyzer for electrophoretic samples has a sample stage movable linearly with respect to a source and a detector of analysis energy. During a first scan of the sample, a voltage is produced representing either the minimum detected fluorescence or the minimum detected optical density. During a second scan, the voltage is combined with the output of the detector to automatically correct the output to a reference.

Electrophoretic analyzer with automatic reference circuit

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Raleigh, NC, United States of America

William E Powell