Honeywell International Inc.

William E Ott

Paul B DuPuis

David L Saunders

Paul B Dupuis

An integrated multi-mode sensor system is described that integrates into a single housing a sensor, signal conditioning circuitry, calibration memory, and interface circuitry that is compatible with both analog and digital end-use circuits. The sensor includes a housing, a sensor circuit, memory, and an interface circuit. The sensor circuit is disposed within the sensor housing, is operable, upon being energized, to supply an output signal that varies with at least one physical parameter to which the sensor circuit is exposed. The interface circuitry disposed within the sensor housing is adapted to receive a mode select signal and the sensor signal. The output circuit is selectively configurable, in response to the mode select signal, to implement one of a plurality of signal processing modes, including analog voltage output, asynchronous pulse density modulation (APDM) and synchronous pulse density modulation (SPDM) of various moduli, and an APDM or SPDM mode using a selectable IC or SPI interface protocol.

Integrated multi-mode sensor

A battery charger charges a plurality of battery portions ( ) connected in series with one another, a battery portion comprising at least one cell. The battery charger includes a battery portion charger ( ) having an output that is electrically floating with respect to a DC power source utilized to power the battery portion charger. The battery portion charger is arranged to be coupled in parallel with a corresponding one of the plurality of battery portions. The battery charger also includes a controller ( ) for controlling the battery portion charger.

Battery charger

A cell buffer with built-in testing mechanism is provided. The cell buffer provides the ability to measure voltage provided by a power cell. The testing mechanism provides the ability to test whether the cell buffer is functioning properly and thus providing an accurate voltage measurement. The testing mechanism includes a test signal-provider to provide a test signal to the cell buffer. During normal operation, the test signal is disabled and the cell buffer operates normally. During testing, the test signal is enabled and changes the output of the cell buffer in a defined way. The change in the cell buffer output can then be monitored to determine if the cell buffer is functioning correctly. Specifically, if the voltage output of the cell buffer changes in a way that corresponds to the provided test signal, then the functioning of the cell buffer is confirmed. If the voltage output of the cell buffer does not change correctly, then the cell buffer is known not to be operating correctly. Thus, the built in testing mechanism provides the ability to quickly and accurately determine if the cell buffer is operating correctly. Furthermore, the testing mechanism provides this functionality without requiring excessive device size and complexity.

Cell buffer with built-in test

A hold-up power supply for flash memory systems is provided. The hold-up power supply provides the flash memory with the power needed to temporarily operate when a power loss exists. This allows the flash memory system to complete any erasures and writes, and thus allows it to shut down gracefully. The hold-up power supply detects when a power loss on a power supply bus is occurring and supplies the power needed for the flash memory system to temporally operate. The hold-up power supply stores power in at least one capacitor. During normal operation, power from a high voltage supply bus is used to charge the storage capacitors. When a power supply loss is detected, the power supply bus is disconnected from the flash memory system. A hold-up controller controls the power flow from the storage capacitors to the flash memory system. The hold-up controller uses feedback to assure that the proper voltage is provided from the storage capacitors to the flash memory system. This power supplied by the storage capacitors allows the flash memory system to complete any erasures and writes, and thus allows the flash memory system to shut down gracefully.

Hold-up power supply for flash memory

A method and apparatus for analog-to-digital conversion is provided that uses pulse width modulation to provide accurate and reliable conversion of analog signals. The methods and apparatus can be implemented in an analog-to-digital converter (ADC) that can meet the requirements of the most demanding environments. Additionally, the ADC can be implemented to provide the high precision needed for many applications. The method and apparatus provides an ADC that converts a received analog input into a pulse width modulated signal with a duty cycle that is responsive to the analog input. The pulse width modulated signal is passed to a duty cycle mechanism that determines the duty cycle of the pulse width modulated signal. The determined duty cycle can then be used to generate a digital value that is proportional to the analog input. The preferred method and apparatus thus provide a reliable and accurate ADC that can be used in a wide range of environments.

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Phoenix, AZ, United States of America

William E Ott