Texas Instruments Corporation

Texas Instruments Incorporated Deutschland, Gmbh

William E Nehrer

Imran Khan

Louis N Hutter

Jozef C Mitros

James Robert Todd

Sameer P Pendharkar

Taylor R Efland

Weidong Tian

Dirk Preikszat

Lou Hutter

James (Bob) Todd

A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate. A PSG layer is disposed outwardly from the polysilicon layer and planarized. The device is pattern etched to form a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer. A dielectric layer is formed in the capacitor channel disposed outwardly from the polysilicon layer. A tungsten plug operable to substantially fill the capacitor channel is formed.

Semiconductor device with an analog capacitor

System and method for forming a semiconductor with an analog capacitor using fewer structure steps

A transistor is formed in a semiconductor substrate. A deep n-well region is used in conjunction with a shallow n-well region. A lightly doped drain extension region is disposed between a drain region and a gate conductor. The use of the regions and against the backdrop of region provides for a very high breakdown voltage as compared to a relatively low channel resistance for the device.

Low leakage power transistor and method of forming

A semiconductor device ( ) comprising a semiconductor substrate ( ) having source and drain regions ( ) located in the semiconductor substrate ( ) and having similar doping profiles, wherein a channel region ( ) extends from the source region ( ) to the drain region ( ). The semiconductor device ( ) also comprises a dielectric layer ( ) located over the source and drain regions ( ), the dielectric layer ( ) having first and second thicknesses (T , T ) wherein the second thickness (T ) is substantially less than the first thickness (T ) and is partially located over the channel region ( ). The semiconductor device ( ) also comprises a gate ( ) located over the dielectric layer ( ) wherein the second thickness (T ) is located between an end ( ) of the gate ( ) and one of the source and drain regions ( ).

EEPROM with reduced manufacturing complexity

The present invention relates to a method for forming an anlog capacitor on a semiconductor substrate. The method comprises forming a field oxide over a portion of the substrate, and forming a polysilicon layer over the field oxide layer, and subsequently forming a silicide over the polysilicon layer. A first interlayer dielectric layer is formed over the substrate, and a capacitor masking pattern is formed. The first interlayer dielectric is etched using the capacitor masking pattern as a mask and the silicide layer as an etch stop, and a thin dielectric is formed over the substrate. A contact masking pattern is formed over the substrate, and a subsequent etch is performed on the thin dielectric and the first interlayer dielectric using the silicide and substrate as an etch stop. A metal layer is deposited over the substrate, and is subsequently planarized, thereby defining an analog capacitor.

Innovative method to build a high precision analog capacitor with low voltage coefficient and hysteresis

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Soquel, CA, United States of America

William E Nehrer