Legerity, Inc.

Silicon Laboratories Inc.

William E Moore

Frank L Thiel

Chris Speyer

Philip S Shiota

Jeremy Charles Smith

Michael G Khazhinsky

Richard Bruce Webb

Anirudh Oberoi

Bruce Webb

Diode circuit layout topologies and methods are disclosed that exhibit reduced lateral parasitic bipolar characteristics at lateral parasitic bipolar circuit emitter edges during ESD or other voltage events as compared to conventional circuit layout topologies. The disclosed diode circuit layout topologies may be implemented to recess parasitic emitter ends relative to surrounding well ties, for example, to reduce or substantially eliminate parasitic bipolar action at lateral emitter edges of the circuitry during ESD events so as to provide higher current threshold for device failure, allowing for smaller device area and/or improved ESD robustness for a given circuit device.

Diode circuit layout topology with reduced lateral parasitic bipolar action

In a particular embodiment, a method of forming a field effect transistor (FET) device having a reduced peak current density is disclosed. The method includes forming a field effect transistor (FET) device on a substrate. The FET device includes a drain terminal, a source terminal, a gate terminal, and a body terminal. The method further includes depositing a plurality of metal contacts along a width of a gate terminal of the FET device and forming a wire trace to contact each of the plurality of metal contacts to reduce a gate resistance along the width of the gate terminal.

Circuit device and method of forming a circuit device having a reduced peak current density

The present invention is generally directed to an optical isolator device, and various methods of making same. In one illustrative embodiment, the method comprises obtaining a single SOI substrate, the SOI substrate having an active layer comprised of silicon and a buried insulation layer, forming a doped layer of silicon above the active layer of the SOI substrate, forming first and second isolated regions in at least the doped layer of silicon, forming a photon generating device in the first isolated region, and forming a photon receiving device in the second isolated region. In one illustrative embodiment, the device comprises a substrate comprised of a bulk layer of silicon, a buried insulation layer formed on the bulk silicon layer, and a doped layer of silicon positioned above the buried insulating layer, first and second isolated regions formed in the doped layer of silicon, a photon generating device formed in the first isolated region, and a photon receiving device formed in the second isolated region.

Optical isolator device, and method of making same

A semiconductor process is disclosed which forms a field plate structure that integrally contacts an emitter region of a bipolar junction transistor by construction, without intervening interconnect layers or contacts. In one embodiment, a single-layer polysilicon electrode forms a field plate electrode which integrally interconnects to a traditional diffused emitter region formed before the polysilicon layer is deposited. This allows for deeper emitter regions required by the deep base regions needed for high-voltage bipolar devices. Moreover, the polysilicon layer, including the polysilicon electrode forming the field plate electrode, may be used as a local interconnect layer.

Bipolar junction transistor incorporating integral field plate

A semiconductor process is disclosed which forms openings in a dielectric layer through which the base region of both high-voltage and high-gain bipolar transistors are formed. In one embodiment of the invention, the openings for the high-gain transistors are first protected by a photoresist layer that is patterned to expose the openings for the high-voltage transistors. A first base implant is performed through the exposed windows in the dielectric layer and into the exposed substrate or epitaxial layer therebelow, and then diffused to a suitable depth. The patterned photoresist is then removed to additionally expose the openings for the high-gain devices, and a second base implant is performed, this time into both base regions, and then diffused to a suitable depth. Emitter regions are then formed within the base regions of both transistor types by traditional implantation and contact techniques. Since the two base implants for each high-voltage transistor are self-aligned to a single opening through the dielectric layer, excellent control and repeatability is achieved for the high-voltage transistors. Moreover, since the second base implant is common to both types of transistors, many of the characteristics of the two types of transistors are well matched to each other.

Self-aligned dual-base semiconductor process and structure incorporating multiple bipolar device types

A semiconductor process is disclosed which forms openings in a dielectric layer through which the emitter region and collector region of lateral bipolar junction transistors are formed. In one embodiment of the invention, the emitter openings for the lateral bipolar junction transistors are first protected by a photoresist layer that is patterned to expose the collector openings for the transistors. A first implant is performed through the exposed windows in the dielectric layer and into the exposed substrate or epitaxial layer therebelow, and then diffused to a suitable depth. The patterned photoresist is then removed to additionally expose the emitter openings, and a second implant is performed, this time into both the collector and the emitter regions, and then diffused to a suitable depth that is shallower than the first implant (used in the collector). Since the two implants are aligned to openings through the dielectric layer defined typically by a single mask, excellent base-width control and repeatability is achieved for the lateral transistors. Through careful selection of the collector and emitter diffusion profiles (i.e., depth and concentration), a more optimal PNP transistor may be constructed that has a collector deeper than its emitter. This scheme provides far greater collection efficiency than a traditional lateral PNP transistor made of the same diffusion for both the emitter and the collector. Greater collection efficiency provides improved Beta, better gain matching, and less parasitic loss of injected holes to a surrounding P-type junction isolation.

Growing community of inventors

Round Rock, TX, United States of America

William E Moore