National Semiconductor Corporation

William E Miller

Christopher M Hall

Richard E Crippen

Robert M Salter, Iii

Gary D Phillips

David W Weinrich

Franklin S Ho

Ying Quan Zhong

Freeman Zhong

A driver circuit limits the magnitude of the initial wave front launched onto a transmission line to a voltage that is approximately one-half of the supply voltage. Thus, immediately after the initial wave front is reflected from an open circuit receiver, a voltage at the receiver is approximately equal to the supply voltage when a rising voltage is launched, and ground when a falling voltage is launched.

Driver circuit that limits the voltage of a wave front launched onto a transmission line

A voltage supply circuit for an LCD driver employs two voltage dividers. A low current voltage divider includes resistive elements having a high resistance, thus providing a bias voltage with a low current. A high current voltage divider includes resistive elements having low resistances, thus providing a bias voltage with a high current. The high current voltage divider provides bias voltage levels with high current at the beginning of each time phase change. Thus, the liquid crystal display receives a high current when updating the bias voltage levels on the LCD, thereby producing a fast settling time. When the bias voltage levels are held constant, however, only the low current voltage divider provides the bias voltage levels to reduce power consumption. A halt mode prevents the liquid crystal display and driver from consuming any power by disconnecting both voltage dividers from the voltage source when in sleep mode. A voltage drop mode produces a reduction in the bias voltage levels by placing another voltage drop in series with the voltage dividers.

Low current voltage supply circuit for an LCD driver

An apparatus for and method of reducing electromagnetic interference of an integrated circuit by providing multiple choking levels are disclosed. A choking circuit includes a choking level select signal generator, a pulse choking circuit connected to the choking level select signal generator, and a modulation control circuit connected to the pulse choking circuit. The choking level is increased when modules of the integrated circuit are less active, which reduces electromagnetic interference. The choking level is decreased when modules of the integrated circuit are more active, which maintains the voltage supplied to the power bus above a desired level.

I.sub.cc current electromagnetic interference choke with multiple

A microprocessor which has a secure read only memory is disclosed. The secure read only memory provides for storage of a program and security to protect that program.

Microprocessor with secure programmable read only memory circuit

An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals. An input data register on the non-volatile memory die and a related multiplexer allows data from different sources to be loaded into the input data register depending on the mode of operation. Also, the output of the input data register is coupled to plural locations so that the destination of the data can also be switched responsive to the mode of operation. Particularly, the output of the input data register is coupled to an output port, a program data register (through which program data can be loaded into the program memory), and a control register for setting various control bits for performing specific integrity tests which can be performed following fabrication. Accordingly, the input data register is used for programming the memory from an external source, setting control bits from an external device, and sending data from the processor to the R port and on to external devices.

Non-volatile memory control and data loading architecture for multiple

An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals. A plurality of feed-throughs are provided on the non-volatile memory die to provide communication paths from the processor die to package pads which are in the shadow of the non-volatile memory die relative to the processor die and thus prevent direct connection from the processor die to the package pad. In normal run mode, these pads are exclusively used as feed-through, providing a direct connection between a specific pad on the processor die and a specific pad on the package. In other modes of operation, however, the signals input from (or output to) the feed-through package pads are re-routed by transfer gates to the non-volatile memory die.

Multiple chip package processor having feed through paths on one die

An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals. The processor includes an in-system programming mode including first and second memory interface control registers on the processor die and the memory die, respectively, for receiving control bits from the processor core for controlling multiplexers on the dies. The various bit output lines of the first memory interface control register are coupled to the control inputs of the multiplexers.

Multiple chip processor architecture with memory interface control

An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals. The processor can be programmed internally or externally. In the in-system programming mode, the processor program counter is used to fetch running instructions out of an on-board ROM instruction memory on the processor die. The processor core outputs an address into which data is to be programmed on its output data bus. The processor core then receives from an external device the data which is to be programmed into the selected address and outputs it serially onto the data bus and therefrom to the memory die. The address and program data are then parallel output from separate registers on the memory die along with a program pulse to program the memory core.

In-system programming architecture for a multiple chip processor

ROM cell programmed ON has N+ source implant spaced a given distance from the gate with LDD bridging the gap between the N+ source and the N channel. ROM cell programmed OFF has P+ implanted into this gap so as to completely override the LDD in this gap. The P+ prevents the N channel from forming ohmic connection to the N+ source.

Method of making semiconductor ROM cell programmed using source mask

An electrostatic discharge ('ESD') protection circuit for use in CMOS I.C. devices provides a low voltage path to and from each input and output ('I/O') pad and power pad by using the wide, low resistance metal VCC and Vss rings and parasitic bipolar transistors configured as three terminal devices at each I/O and power pad. The present invention also provides a clamp, between the VCC and VSS rings, capable of being rapidly switched into the conducting state during an ESD event so as to shunt excess bias current that could otherwise damage reverse biased junctions during an ESD event.

Electrostatic discharge protection for CMOS integrated circuits

A switching element is connected to an integrated circuit for shunting an ESD pulse away from the integrated circuit features. A plurality of detection circuits responsive to typical ESD waveform characteristics provide logical control of the switching means. In the preferred embodiment, a NAND gate drives the switching element. The first input to the NAND gate is a first RC network having a first time constant that exceeds the characteristic rise time of the typical ESD pulse, but not the characteristic duration of the typical ESD pulse. The second input to the NAND gate is a feedback loop from the NAND gate output. The feedback loop includes a second RC network having a second time constant that exceeds the duration of a noise pulse, a third RC network having a third time constant that approximates the characteristic duration of the typical ESD pulse, and an inverter between the second and third RC networks. Application of the ESD pulse causes the first input to drive the NAND gate, thus turning on the switching element, and if the ESD pulse is still present when the second time constant is exceeded, the switching means is latched on via the second input until the third time constant is exceeded.

Electrostatic discharge detection and clamp control circuit

Semiconductor ROM cell programmed using source mask

A single resistance permits a CMOS driver to have output devices that controllably transition 'fast off-slow on' and which are not simultaneously on while the driver switches states. The driver's output and supply currents contain reduced harmonics. The resistance is coupled to the gates of the output stage PMOS-NMOS devices, and forms an RC circuit with the intrinsic capacitance at the gates, extending the turn-on transition of the gate drive voltages. Each output device then turns on relatively slowly, but turns off normally. The output current transition times are essentially determined by the resistance and intrinsic capacitances. The resistance is implemented using polysilicon or diffusion, and preferably has a magnitude ten times the on-channel resistance of the input PMOS and NMOS devices driving the output stage. Because the resistance and intrinsic capacitances are essentially temperature and power supply voltage independent, and but slightly process dependent, the current output transition times can be controlled despite CMOS parameter variations. A 3-state embodiment of the CMOS buffer uses parallel coupled PMOS-NMOS devices to switchably couple in the resistance between both output gates when the enable signal is high. Second input PMOS and NMOS devices, connected in parallel across the first input PMOS and NMOS devices, turn on across the first input devices when the enable signal is low. A high enable signal enables the driver circuit, while a low enable signal uncouples the resistance and turns off both output PMOS and NMOS devices, putting the circuit's output in a high impedance state.

CMOS output driver with transition time control circuit

Method for late programming of MOS integrated circuit devices. A second or third level conductive layer is used as a device selection mask for transporting dopant from a doped gate (formed from a first level conductive layer) into the channel region of selected field effect transistors.

Method of late programming MOS devices

A field effect transistor has its drain and source regions connected between one of the two supply pads of an operative integrated circuit, the gate of the field effect transistor being connected to the other pad such that the gate is negatively biased during reverse battery to prevent current flow through the circuit in this condition and, hence, to prevent destruction of the circuit. The FET is sized to have minimal voltage drop during normal, forward battery operation of the circuit. The FET can be implemented as either an N-channel or a P-channel device.

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Los Gatos, CA, United States of America

William E Miller