Raytheon Company

William E Hoke

Jeffrey R LaRoche

Katerina Y Hur

Eduardo M Chumbes

Ralph Korenstein

Theodore D Kennedy

Steven D Bernstein

Brian D Schultz

Daniel P Resler

John J Mosca

Peter S Lyman

Rebecca McTaggart

Peter J Lemonias

Lindley T Specht

James Carter

Kevin Iliff McCarthy

Thomas E Kazior

Colin Steven Whelan

Kelly P Ip

Shahed Reza

Kamal Tabatabaie

James M Elliott

Philbert Francis Marsh

Abbas Torabi

Dale M Shaw

Noren Pan

H Jerrold Van Hook

Amanda Kerr

Vilnis G Kreismanis

Richard Traczewski

Steven K Brierley

Jeffrey R Laroche

Katerina Hur

Kevin Mccarthy

A structure having: a nucleation layer; and a Group III-Nitride structure disposed on a surface of the nucleation layer, the Group III-Nitride structure comprising a plurality of pairs of stacked Group III-Nitride layers, each one of the pairs of layers having a lower layer having a 3D growth structure and each one of the upper one of the pairs of layers having a 2D growth structure. Each one of the lower layers at completion has a surface roughness greater than a surface roughness at completion of an upper one of the pair of layers. Interfaces between each one of the upper layers and each one of the lower layers of the plurality of pairs of stacked Group III-Nitride layers have crystallographic dislocation combinations and/or annihilations therein.

Group III-nitride structure having successively reduced crystallographic dislocation density regions

A semiconductor structure having a Group III-N buffer layer and a Group III-N barrier layer in direct contact to form a junction between the Group III-V buffer layer the Group III-N barrier layer producing a two dimensional electron gas (2DEG) channel, the Group III-N barrier layer having a varying dopant concentration. The lower region of the Group III-N barrier layer closest to the junction is void of intentionally introduced dopant and a region above the lower region having intentionally introduced, predetermined dopant with a predetermined doping concentration above 1&#xd7;10atoms per cm.

Doped barrier layers in epitaxial group III nitrides

A method for forming a structure on a surface of a semiconductor. The method includes: forming the material as a lower layer of the structure using a first deposition process to provide the lower layer with a first etch rate to a predetermined etchant; forming the upper layer of the structure with the material on the lower using a second deposition process to provide the upper layer with a second etch rate to the predetermined etchant higher than the first etch rate; and applying the predetermined etchant to upper layer to selectively remove the upper while leaving the lower layer.

Semiconductor structure with layers having different hydrogen contents

A semiconductor structure having a silicon substrate having a &#x3c;111&#x3e; crystallographic orientation, an insulating layer disposed over a first portion of the silicon substrate, a silicon layer having a &#x3c;100&#x3e; orientation disposed over the insulating layer, and a non-nitride column III-V semiconductor layer or column II-VI semiconductor layer having the same &#x3c;111&#x3e; crystallographic orientation as the silicon substrate, the non-nitride column III-V semiconductor layer or column II-VI semiconductor layer being in direct contact with a second portion of the silicon substrate. A column III-nitride is disposed on the surface of the third portion of the substrate.

Semiconductor structure having silicon devices, column III-nitride devices, and column III-non-nitride or column II-VI devices

A semiconductor structure having mesa structure comprising: a lower semiconductor layer; an upper semiconductor layer having a higher band gap than, and in direct contact with, the lower semiconductor layer to form a two-dimension electron gas (2DEG) region between the upper semiconductor layer. The 2DEG region has outer edges terminating at sidewalls of the mesa. An additional electron donor layer has a band gap higher than the band gap of the lower layer disposed on sidewall portions of the mesa structure and on the region of the 2DEG region terminating at sidewalls of the mesa. An ohmic contact material is disposed on the electron donor layer. In effect, a sideway HEMT is formed with the electron donor layer, the 2DEG region and the ohmic contact material increasing the concentration of electrons (i.e., lowering ohmic contact r&#xe9;sistance) all along the contact between the lower semiconductor layer and the electron donor layer.

Gallium nitride devices having low ohmic contact resistance

Described herein is a liquid crystal (LC) device having Gallium Nitride HEMT electrodes. The Gallium Nitride HEMT electrodes can be grown on a variety of substrates, including but not limited to sapphire, silicon carbide, silicon, fused silica (using a calcium flouride buffer layer), and spinel. Also described is a structure provided from GaN HEMT grown on large area silicon substrates and transferred to another substrate with appropriate properties for OPA devices. Such substrates include, but are not limited to sapphire, silicon carbide, silicon, fused silica (using a calcium fluoride buffer layer), and spinel. The GaN HEMT structure includes an AlN interlayer for improving the mobility of the structure.

Gallium nitride for liquid crystal electrodes

A semiconductor structure having compound semiconductor (CS) device formed in a compound semiconductor of the structure and an elemental semiconductor device formed in an elemental semiconductor layer of the structure. The structure includes a layer having an elemental semiconductor device is disposed over a buried oxide (BOX) layer. A selective etch layer is disposed between the BOX layer and a layer for a compound semiconductor device. The selective etch layer enables selective etching of the BOX layer to thereby maximize vertical and lateral window etch process control for the compound semiconductor device grown in etched window. The selective etch layer has a lower etch rate than the etch rate of the BOX layer.

Method and structure having monolithic heterogeneous integration of compound semiconductors with elemental semiconductor

Described herein is a liquid crystal (LC) device having Gallium Nitride HEMT electrodes. The Gallium Nitride HEMT electrodes can be grown on a variety of substrates, including but not limited to sapphire, silicon carbide, silicon, fused silica (using a calcium fluoride buffer layer), and spinel. Also described is a structure provided from GaN HEMT grown on large area silicon substrates and transferred to another substrate with appropriate properties for OPA devices. Such substrates include, but are not limited to sapphire, silicon carbide, silicon, fused silica (using a calcium fluoride buffer layer), and spinel. The GaN HEMT structure includes an AlN interlayer for improving the mobility of the structure.

A semiconductor structure having: a silicon substrate having a crystallographic orientation; an insulating layer disposed over the silicon substrate; a silicon layer having a different crystallographic orientation than the crystallographic orientation of the substrate disposed over the insulating layer; and a column III-V transistor device having the same crystallographic orientation as the substrate disposed on the silicon substrate. In one embodiment, the column III-V transistor device is in contact with the substrate. In one embodiment, the device is a GaN device. In one embodiment, the crystallographic orientation of the substrate is &#x3c;111&#x3e; and wherein the crystallographic orientation of the silicon layer is &#x3c;100&#x3e;. In one embodiment, CMOS transistors are disposed in the silicon layer. In one embodiment, the column III-V transistor device is a column III-N device. In one embodiment, a column III-As, III-P, or III-Sb device is disposed on the top of the &#x3c;100&#x3e; silicon layer.

Structure having silicon CMOS transistors with column III-V transistors on a common substrate

A heterostructure having a heterojunction comprising: a diamond layer; and a boron aluminum nitride (BAlN) layer disposed in contact with a surface of the diamond layer, where x is between 0 and 1.

Boron aluminum nitride diamond heterostructure

Apparatus and method for growing and observing the growth of epitaxial layers on a wafer. The apparatus includes: epitaxial growth apparatus; a source of light mounted to illuminate an entire surface of the wafer in the apparatus during growth of the epitaxial layer on the entire surface of the wafer; and apparatus for observing scattering of the light from the entire surface of the wafer during growth of the epitaxial layer on the entire surface of the wafer. The method includes growing the epitaxial layer on a surface of the wafer and observing scattering of the light from the entire surface of the wafer during growth of the epitaxial layer on the entire surface of the wafer. The growing process is varied in accordance with the observation. With an epitaxial layer of gallium nitride (GaN) the entire surface of the wafer is observed for balls of gallium.

Method for continuous, in situ evaluation of entire wafers for macroscopic features during epitaxial growth

A semiconductor structure, comprising: a substrate; a first aluminum nitride (AlN) layer having an aluminum/reactive nitride (Al/N) flux ratio less than 1 disposed on the substrate; and a second AlN layer having an Al/reactive N flux ratio greater than 1 disposed on the first AlN layer. The substrate is a compound of silicon wherein the first AlN layer is substantially free of silicon.

Gallium nitride high electron mobility transistor structure

A transistor structure having an gallium arsenide (GaAs) semiconductor substrate; a lattice match layer; an indium aluminum arsenide (InAlAs) barrier layer disposed over the lattice match layer; an In Ga As lower channel layer disposed on the barrier layer, where y is the mole fraction of In content in the lower channel layer; an In Ga As upper channel layer disposed on the lower channel layer, where x is the mole fraction of In content in the upper channel layer and where x is different from y; and an InAlAs Schottky layer on the In Ga As upper channel layer. The lower channel layer has a bandgap greater that the bandgap of the upper channel layer. The lower channel layer has a bulk electron mobility lower than the bulk electron mobility of the upper channel layer where.

Split-channel high electron mobility transistor (HEMT) device

A semiconductor structure is provided having a III-V substrate, a buffer layer over the substrate, such buffer layer having a compositional graded quaternary lower portion and a compositional graded ternary upper portion. In one embodiment, the lower portion of the buffer layer is compositional graded AlGaInAs and the upper portion is compositional graded AlInAs.

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Wayland, MA, United States of America

William E Hoke