At+t Corp.

William E Feger

Paul W Rutkowski

A Boundary-Scan cell (12') for facilitating testing of an electronic device (10), includes a system flip-flop (30') interposed between an output buffer (18) of the device and an internal logic block (14) which drives the buffer. The system flip-flop has asynchronous clear and preset capability which allows the flip-flop to be cleared or preset as necessary so that its output bit reflects a bit previously latched in the Boundary-Scan cell during testing. During non-testing intervals, the preset and clear capability of the system flip-flop (30') is disabled to allow the flip-flop to pass a bit between the internal logic of the device and the output buffer without undue propagation delays.

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Macungie, PA, United States of America

William E Feger