International Business Machines Corporation

William E Dougherty, Jr

Stuart E Greer

Zhuo Li

Charles Jay Alpert

James N Humenik

Stephen Thomas Quay

Jose Luis Neves

Ying Zhou

James J Curtin

Douglas S Search

Lawrence V Gregor

Irving Feinberg

William J Nestork

Morton D Reeber

Alan Platt

Robert W Sargent

William T Norris

Thomas F Redmond

Donald L Klein

A mechanism is provided for addressing coupled noise-based violations. For each net in an integrated circuit (IC) design, a determination is made as to whether an associated delta wire delay is below a predetermined threshold. Responsive to the associated delta wire delay failing to be below the predetermined threshold, a subset of nets is formed. For each net in the subset of nets, a stage delay side model of the net is adjusted to emulate a noise impact on timing of the net and an optimization is applied using the stage delay side model of the net. A full retiming of the set of nets is then performed. For each net in the subset of nets a determination is made as to whether the net has degraded slack and, responsive to the net having degraded slack, the applied optimization is backed out.

Addressing coupled noise-based violations with buffering in a batch environment

A method for eliminating negative slack in a netlist representing a chip design uses a contrived timing environment to overlay information onto the design environment during logic and physical synthesis phase. The overlaid timing information determines which netlist transformation provides a maximum leverage for the negative slack elimination and a way for creating a dynamic transformation recipe tuned for each design. The method further provides upper bounds on the negative slack elimination to prevent the netlist transforms from being applied to situations exceeding the capabilities for improving the design.

Method for eliminating negative slack in a netlist via transformation and slack categorization

A substrate for packaging semiconductor chips is provided which is structured with conductors having opposite ends terminating in a mounting surface and intermediate portions extending beneath the surface. The ends of the conductors are arranged in repeating patterns longitudinally along the substrate separated by orthogonal strips free of conductor ends to allow for dense surface wiring. The repeating patterns are arranged to allow for chip mounting sites having sufficient spacing to allow for surface wiring. In this way chips in the same and repeat pattern can be connected by personalized surface wiring and preset substrate conductors.

Personalizable masterslice substrate for semiconductor chips

A method of making an aperture of a predetermined shape into a dielectric substrate which will lockingly receive a deformable contact pin. It includes providing a dielectric material which shrinks in response to a heat treatment by an amount which is different in one direction from that in another direction, and which irreversibly changes dimensions in its two orthogonal directions in proportion to this difference. An aperture is formed in such a material, in a direction normal to the plane of the two orthogonal directions and the material is subjected to a heat treatment that causes a differential shrinkage in the aperture and a change in the shape of the aperture. A deformable contact pin is then forced into a locking position in the aperture. By using such a method to lock a contact pin in close proximity to a conductive line extending across the substrate or by having the aperture and the pin extend through the substrate, electrical circuits on one side of the substrate can be contacted through a contact pin on the opposite side of the substrate.

Method for providing improved electrical and mechanical connection

A decoupling capacitor for mounting on an integrated circuit multi-layer ceramic. A bottom layer electrode, is evaporated or sputtered onto a carrier. A high dielectric layer is deposited followed by the upper metallurgy and a top isolating layer. Via holes are etched to respective electrode layers, BLM deposited thereon followed by solder balls. The electrode is mounted onto the substrate, solder balls face down in contact with a compatible footprint.

Thin film discrete decoupling capacitor

In a process for producing a ceramic substrate for use in an electrical packaging structure, according to which (1) a substantially homogeneous ceramic mass, comprising alumina or glass ceramic, an organic bonding agent, a plasticizing agent, an emulsifying agent, a glass frit, and a solvent, is formed into a cohesive flat strip, (2) said strip is green dried and cut into desired size substrates, and (3) said substrates are sintered, the improvement comprising the step of lapping the substrates prior to the sintering step, whereby, after sintering, a smoother surface is obtained on said substrates than is obtained with substrates that have not been so lapped.

Process for producing smoother ceramic surfaces

Repair of opens and shorts in semiconductor packages and chip metallurgy by initial conversion of shorts into opens by severing of lines about the shorts, followed by interconnection of conductor patch lines to the good circuit portions through an insulating layer.

Fine line repair technique

The coating of a conductor pattern on dielectric green sheets to a common edge thereof with stacking or superimpositioning together of a plurality of sheets to enclose the conductor pattern followed by sintering, with the edge side of the fired body having the exposed end terminations becoming the actual face of the body on which a semiconductor device is mounted in electrical circuit connection to respective ones of the common end terminations of the conductor runs. The conductor runs are returned through the body to the active face of the body to position the opposite or distal ends of the conductors thereat, in an increased spaced relationship of the distal conductor terminations. For external connection, terminal pins may be embedded in the fired body for connection at adjacent and to the distal conductor termination, with the pins projecting therefrom.

Multi-layer dielectric planar structure having an internal conductor

The coating of a conductor pattern on dielectric green sheets to a common edge thereof with stacking or superimpositioning together of a plurality of sheets to enclose the conductor pattern followed by sintering, with the edge side of the fired body having the exposed end terminations becoming the actual face of the body on which a semiconductor device is mounted in electrical circuit connection to respective ones of the common end terminations of the conductor runs. The opposite or distal ends of the conductor runs may be fanned out to the opposite edge of side of the fired body in increased spaced relationship to each other.

Multi-layer dielectric structure

A device for removing contaminant impurities, particularly contaminants existing at very low levels, from a liquid, including a heating element at least partially immersible in the liquid, a confinement means at least partially immersible in the liquid for maintaining a pulsating bubble of vapor of the liquid, the heating element located within the confining means, openings in the confining means to allow periodic partial escape of the vapor bubble and ingress of liquid.

Growing community of inventors

Poughkeepsie, NY, United States of America

William E Dougherty, Jr