Advanced Micro Devices Corporation

Google Inc.

William Dow Heavlin

Zoran Krivokapic

David F Kyser

Wolf-Dietrich Weber

Ankit Somani

Ana Radovanovic

Matthew D Wytock

Richard C Kittler

Ping Wen

Seungil You

A thermostat management server may include one or more processors and one or more memory devices comprising instructions that, when executed by the one or more processors, cause the one or more processors to perform operations comprising receiving information that characterizes energy usage associated with the plurality of thermostats, receiving parameters characterizing proposed future demand-response events, selecting a combination of thermostats from the plurality of thermostats for which the energy usage can be reduced, simulating a demand response event based on the parameters and using different weather conditions for the combination of the plurality of thermostats, generating statistical probabilities of meeting a plurality of capacity reduction levels based on the different weather conditions, selecting a capacity reduction level from the plurality of capacity reduction levels based on the statistical probabilities, and sending the capacity reduction level to the utility provider computer system.

Dispatch engine for optimizing demand-response thermostat events

A method for a systematic approach to forming experimental designs for large, complex systems after an idea for a product is formed. Critical variables for the product are determined by experts in the field, a design matrix Uis defined, a base design matrix X is generated, Y(P)=(I&#x2212;B(BB)B)[(XP)//U]A & Wynn's criterion is defined, where P is a permutation matrix, I is an identity matrix, B is a blocking matrix, Bis a transposed matrix of B and A is a matrix composed of causal map-based coefficients and wherein a design matrix Uis created. The index k&#x2190;k+1 is set and an algorithm to choose the best of random column permutation matrices P and an algorithm to choose the best column permutation matrix P that is near a previous solution and setting U&#x2190;[XPwith rows from Uappended].

Experimental design for complex systems

A method of defining a toleranced process based on a nominal process, applicable to any manufacturing process wherein the output is dependent on a process having a number of input factors which are subject to variation, and have a mean and standard deviation. The method comprises the steps of: representing the variability of the response of a system to the actual distribution of at least one of said factors and parameterized by at least one parameter; performing at least one step in the manufacturing process for a given lot of wafers; evaluating actual variability and nominal variability of said components against a schedule of parameters in an array; modeling the output of the evaluation to determine the manner in which to continue processing of the lot.

Lot specific process design methodology

When Tilted Channel Implant (TCI) is performed on transistor precursor structures having an etch-defined gate length (L ) and a trim-defined sidewall thickness (S ), mass production deviations may cause errors and cause shifts in the lateral placement and implant depth of TCI dopants. Countering adjustments to TCI dosage and TCI energy are automatically made in accordance with the invention. In one embodiment, a first linear or quasi-linear interpolation function is used having form: Energy &equals;E *(1&plus;&bgr;*e /S ), where multiplying factor &bgr; may either be a constant or a function of normalized sidewall error value, e /S . In the same embodiment, a second linear or quasi-linear interpolation function is used having form: Dose &equals;Dose *(1&plus;&agr;(L &minus;L )/L ), where multiplying factor &agr; is a constant or a function of normalized gate length error value, (L &minus;L )/L .

Feed-forward control of TCI doping for improving mass-production-wise statistical distribution of critical performance parameters in semiconductor devices

When Tilted Channel Implant (TCI) is performed on transistor precursor structures having an etch-defined gate length (L ) and a trim-defined sidewall thickness (S ), mass production deviations may cause errors between targeted values for these critical dimensions (CD's) and the correspondingly measured CD's. These deviations may respectively cause shifts in the lateral placement of TCI dopants or in the depth of implant of the TCI dopants, thereby tending to cause variation in final device characteristics. Countering adjustments to TCI dosage and TCI energy are automatically made in accordance with the invention. These countering adjustments in the TCI process enable expansion of tolerance ranges in pre-TCI production steps, thereby increase manufacturing yield.

Feed-forward control of TCI doping for improving mass-production-wise, statistical distribution of critical performance parameters in semiconductor devices

Identification of within-wafer and wafer-to-wafer variations in yield induced by processing steps in a multi-step manufacturing process. Methods are implemented along with wafer position tracking for process control of the manufacturing process. Wafers are systematically rotated according to their position in a batch before entering a processing step. Wafer position tracking analysis of rotated wafers advantageously reveals a static pattern on each wafer regardless of position in a batch. Alternatively, data reduction methods provide a compact representation of site-specific yield data. The data reduction methods use multidimensional scaling to determine distance factor scores and angle factor scores. The distance factor scores track changes in pattern on the wafers. Wafers similar in pattern regardless of rotation angle have similar distance factor scores. The angle factor scores track rotation of patterns on wafers. Analysis of scatter plots enables a process operator to determine which processing step is responsible for variations in yield.

Methods for identifying sources of patterns in processing effects in manufacturing

A method of defining a toleranced process based on a nominal process, applicable to any manufacturing process wherein the output is dependent on a process having a number of input factors which are subject to variation, and have a mean and standard deviation. The method comprises the steps of: representing the variability of the response of a system to the current variability of at least one of the factors and at least one tightening factor; evaluating the components against a schedule of tightening factors in an array; modeling the output of the evaluation using interpolation to determine a mathematical function defining the toleranced process; and applying at least one of the models to a fabrication system to complete the toleranced process.

Statistical process window design methodology

The present invention provides for more realistic worst case extreme determinations for an integrated circuit as compared to conventional techniques. In particular, the present invention provides a framework which affords for improved linkage between semiconductor manufacturing process parameters and an integrated circuit designed based on the electrical properties of cells making up the integrated circuit. The present invention divides an integrated circuit into simple standard cells and more complex cells. For simple standard cells (e.g., XOR, NAND, NOR, inverter), a pre-modeling step is performed to model the simple standard cell as a circuit in order to obtain gate delay and power consumption distributions related thereto. Such pre-modeling affords for more accurate semiconductor physical parameters to be employed to generate the normalized distribution of the integrated circuit which in turn provides for better worst case extremes. More complex cells are modeled with I/V curves distributions for understanding the effects of semiconductor device attribute choices, such as channel length, effects of &ldquo;guard band&rdquo; or manufacturability of such devices. As a result of the present invention, IC circuits may be manufactured with more realistic or practical worst case extreme parameters and thus, more densely designed and manufactured without substantially sacrificing operability.

Worst case design parameter extraction for logic technologies

A design apparatus, article of manufacture, method and system are disclosed for simulating mass-produced semiconductor device behavior. Drain-to-source current values are obtained from actual semiconductor devices in response to voltage levels at the drain-to-source and gate of a semiconductor device. Semiconductor device attributes, such as channel-length doping concentration are also measured. A device simulator and process simulator are calibrated based upon the actual drain-to-source current values and measured attributes. A process simulator is run in response to simulated process parameters to obtain a plurality of simulated mass-produced semiconductor devices having varying semiconductor attributes. A device simulator is then run using the plurality of simulated mass-produced devices to obtain a plurality of I/V curves based upon the plurality of simulated semiconductor devices. Worst-case I/V curves are then obtained from the plurality of I/V curves by analyzing drain-to-current values in the plurality of I/V curves associated with a predetermined voltage value. Parameters then may be extracted from the worst-case I/V curves in order to determine accurate worst-case semiconductor device designs. Manufacturing guard bands may then also be identified based upon the worst-case I/V curves and idealized I/V curves.

Apparatus, article of manufacture, method and system for simulating a

A computer is used to estimate a fabrication yield for a semiconductor product under design which includes a plurality of integrated circuit dies, each of which includes a memory cache having a predetermined redundancy scheme in the form of redundant rows and/or columns. A bitmap failure analysis of an existing semiconductor product including a plurality of integrated circuit dies having bitmap failure modes that are comparable to those of the product being designed is performed to obtain a number of failed caches. An observed repair rate is computed as a ratio of a number of the failed caches that can be repaired by the predetermined redundancy scheme to the number of failed caches. A model repair rate for the predetermined redundancy scheme which approximates the observed repair rate is computed using a multiple Poisson model including computed average numbers .lambda. of failures for the failure modes respectively. The numbers .lambda. are optimized by minimizing a least squares difference between the observed repair rates and the model repair rates. The fabrication yield is computed as a predetermined function of the model repair rate including scale factor(s) for the circuit on the wafer being designed. The method can be used to select a redundancy scheme for the wafer by computing fabrication yields for a plurality of candidate redundancy schemes, and selecting the redundancy scheme which has the highest return for additional test, manufacturing and design investment.

Computer implemented method for estimating fabrication yield for

A system and a method for designing, fabricating and testing multiple cell test structures validate a cell library. Each test structure includes a plurality of logic layers where outputs of a logic layer are connected only to the inputs of a succeeding logic layer. In contrast to the conventional design method, mismatches in each logic layer are increased to assure extreme conditions in the test structure. For each logic layer, the number of fan-outs of each output from the previous logic layer is specified, and the number of basic cells in each layer is based on the number of inputs of the test structure. Based on D-optimality and maximum fan-in resolution, an assignment for connecting each fan-out and each fan-in is determined. Alternatively, a design repair algorithm can be used to make such an assignment. Each output of each logic cell in the logic layer is then assigned a length using D-optimality. The predicted propagation delays of a designed test structure are compared to the actual propagation delays of a fabricated test structure. The above is repeated for designing, fabricating, and testing multiple cell test structures to validate the cell library.

System and method for designing, fabricating and testing multiple cell

A method and system are disclosed for: (a) matching a machine-implemented process simulator with an actual fabrication line, (b) using the matched model to simulate the statistical results of mass production by the modeled production line, (c) using the model to predict cross-reticle variance from collected data for in-scribe features, (d) using the model to decompose the variance contributions of each process parameter and identify the more prominent contributors, and (e) using the model to identify the process parameter adjustments which would provide best leverage when taken one at a time.

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El Granada, CA, United States of America

William Dow Heavlin