International Business Machines Corporation

William Dennis Williams

Michael T Benhase

Gail Andrea Spear

Brent Cameron Beardsley

Said Abdullah Ahmad

Steven Robert Lowe

Kevin J Ash

Carol Santich Mellgren

Kenneth Wayne Todd

Thomas Charles Jarvis

Sam Clark Werner

David Frank Mannenbach

Vernon John Legvold

A data coherence system includes a generation number written to a data track of a logical sub-system. The generation number is compared to a corresponding generation number in a processing device when it is initialized. If the two generations numbers are the same, the generation numbers are incremented and saved. If not, cache associated with the logical sub-system residing within the processing device is erased and the generation numbers are reset.

Data coherence system

Provided are a method, system, and program for maintaining data in a first cache and second cache, wherein a backup cache maintains a backup copy of data in the first cache, and wherein the first cache is used to cache a first set of data in a storage system and the second cache is used to cache a second set of data in the storage system. An unavailable state of the first cache is detected. In response to detecting the unavailable state, requests to the first set of data are blocked and at least one space in the second cache is allocated for data in the backup cache. Requests to the first set of data are allowed to proceed after the at least one space is allocated in the second cache and before the data in the backup cache is copied to the at least one allocated space in the second cache. The data from the backup cache is copied to the allocated at least one space in the second cache after the requests to the first set of data are allowed to proceed.

Method, system, and program for restoring data in cache

Provided are a method, system, and program for increasing processor utilization. A list of work is divided for processing among a plurality of processes, wherein a process is allocated a part of the list of work to process, and the processes execute in parallel. If a process completes the list of work allocated to the process then the process is made available on an available process queue. Before a process performs any work, the process reads the available process queue and determines if any process is available to share the work. If so, the work is split up between the examining process and the available process. In one implementation, the work involves scanning a cache and if necessary destage data.

Method, system, and article of manufacture for increasing processor utilization

The peripheral cache DASD subsystem is connected to predetermined host processors. A channel connection between the host processor and the peripheral subsystem has a much higher burst rate then the burst data transfer rate of a DASD while having an extended signal propagation time preventing rapid exchanges of interactive control signals. The branch write occurs in that data is written both to the DASD and to the cache simultaneously. The write domain is established in the subsystem by the host processor as a number of records to be written on the DASD only after the available cache space is compared with a needed cache space for the entire write domain. Whenever the available cache space is less than the write domain needs, then the peripheral cache DASD subsystem subsets the data transfer into a plurality of subset data transfers each having data storable in the available cache data storage space. Calculations for determining the maximum cache space are described and sets of machine operations are disclosed for effecting the above operations.

Method for operating a cached peripheral data storage subsystem

Growing community of inventors

Tucson, AZ, United States of America

William Dennis Williams