Texas Instruments Corporation

William David Smith

Marco Corsi

Robert Floyd Payne

William J Bright

David Leonard Larkin

Martin Kithinji Kinyua

George Ernest Harris

Philip M Pratt

Apparatus and methods disclosed herein operate to compensate for skew between inverse phases (e.g., differential phases) of an analog signal appearing at the inputs of an analog signal capture circuit such as a track-and-hold or sample-and-hold circuit associated with an ADC or similar device. Each of two capture clocks is used to capture one of the inverse phases. One or more delay circuits are configured to create a differential delay between clock transitions associated with the two capture clocks. The differential delay is proportional to the input skew between the inverse phases. The phases are consequently sampled at substantially identical points on a phase domain axis. Embodiments operate to create phase sampling synchronicity and to thereby decrease the amplitude of a common-mode signal component that results from the skew. Increased linearity and decreased distortion may result.

Timing skew error correction apparatus and methods

An analog-to-digital converter apparatus has a plurality of stages. Each stage includes a residue amplifier having a first and second amplifier unit. Each of the amplifier units has a first input locus, a second input locus and an output locus. The amplifier units cooperate in receiving a differential input data signal at the first input loci. A DC level setting signal unit is coupled with the second input loci and provides a DC level setting current in a first current direction. A counter-current signal generating unit is coupled with the second input loci via a single coupling locus common with the second input loci and provides a control current signal to the second input loci in a second current direction opposite to the first current direction. The control current signal provides a DC level control for each of the amplifier units.

Method and apparatus for reducing noise in analog-to-digital converter devices

A method for decreasing CHC degradation is provided. The method includes providing a semiconductor device ( ) having at least one metal layer ( ) completed. Then, a planarizing dielectric layer ( ) is added to the semiconductor device ( ). The semiconductor device ( ) is heated in a hydrogen rich environment until hydrogen completely saturates the semiconductor device ( ).

Method for decreasing CHC degradation

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Allen, TX, United States of America

William David Smith