National Semiconductor Corporation

Fairchild Semiconductor Corporation

Tripath Technology, Inc.

Other

William David Llewellyn

Robert J Strain

Ha Chu Vu

Seema Varma

Philip Crawley

Majid Shushtarian

Cary L Delano

Earl Schreyer

Chungwai Benedict Ng

Carmine Cozzolino

Nghiem Nguyen

Kunhong Qu

In one general aspect, a method can include calculating, at a calibration temperature of a speaker, a calibration parameter through a coil of the speaker in response to a first test signal, and can include sending a second test signal through the coil of the speaker. The method can also include measuring a parameter through the coil of the speaker based on the second test signal, and calculating a temperature change of the coil of the speaker based on the parameter and based on the calibration parameter at the calibration temperature.

Methods and apparatus related to protection of a speaker

Protection of a speaker using temperature calibration

Devices and methods provide a voltage regulating device including voltage supply circuitry configured to receive a first voltage, generate at least a second voltage based on the first voltage, and output an output voltage, the output voltage being one of the first voltage and the second voltage based on a voltage selection signal; regulator circuitry configured to switch between the output voltage and a reference potential based on a control signal; and control circuitry configured to generate the control signal, the control signal having a first duty cycle if the output voltage is the first voltage and a second duty cycle if the output voltage is the second voltage, the control circuitry configured to adjust the second duty cycle based on, at least in part, a droop voltage in the regulator circuitry.

Dual-mode voltage doubling buck converter with smooth mode transition

An apparatus includes a capacitor, a current generating circuit communicatively coupled to the capacitor, and a current pulse timing circuit communicatively coupled to the current source circuit. The current timing pulse circuit is configured to time durations of a first plurality of current pulses from the current generating circuit for charging the capacitor and a second plurality of current pulses for discharging the capacitor, and step the durations of the current pulses between a minimum duty cycle and a maximum duty cycle. A cycle of providing the first plurality of current pulses and providing the second plurality of current pulses results in generation of a subsonic pseudo-sinusoidal pulse signal at the capacitor.

Subsonic test signal generation technique

This document discusses, among other things, a modulator including a first integrator configured to receive an input signal and a first feedback signal from an output stage, a second integrator configured to receive an output of the first integrator and a second feedback signal, and a comparator configured to be coupled to a regulated supply voltage, to receive an output of the second integrator and a modulation signal, and to provide a pulse width modulated representation of the input signal. The output stage is configured to be coupled to an unregulated supply voltage, and the second feedback signal can include a representation of an output of the comparator configured to reduce artifacts in the pulse width modulated representation of the input signal induced by changes in an amplitude of the unregulated supply voltage.

Class D pulse width modulator with dual feedback

This document discusses apparatus and methods for configuring and providing crosstalk cancellation to maintain channel separation in a multi channel system. In an example, an amplifier circuit can include a crosstalk cancellation circuit configured to reduce crosstalk from a first output to a second load and from a second output to a first load where the first load and the second load share a return path.

Amplifier crosstalk cancellation technique

This document discusses, among other things, a system and method for reducing electromagnetic interference of a switched signal. In an example, a switched input signal can be received at an input and a transition rate of an edge rate controlled, switched output signal can be controlled in response to the received switched input signal.

Edge rate control

A drive current direction between first and second amplifiers can be selected using a received indication of an output current in an at least partially reactive load, and an amplified output signal can be produced using the selected drive current direction and the first and second amplifiers. Further, the first and second amplifiers can be configured to alternate between a pull-up mode and a pull-down mode, each amplifying half of a full wave output signal.

Amplifier current drive reversal

Circuits, devices, and methods for enabling the digitization of scanned images with an Analog Front End (AFE) circuit. The AFE circuit includes a sampler for sampling a signal produced by an image sensor and in response generating analog image samples. The AFE circuit also includes a Programmable Gain Amplifier for generating amplified samples by amplifying the analog image samples. The AFE circuit further includes an Analog to Digital Converter for generating digitized samples from the amplified samples; and a Digital Programmable Gain Amplifier for amplifying the digitized samples which are subsequently presented to a processor for further processing of the scanned image. Accordingly, the scanned image is digitized with amplification taking place both in the analog and in the digital domain, deriving benefits from each. The AFE circuit may be calibrated in two steps, once for each of the domains.

Programmable gain amplifier with hybrid digital/analog architecture

A method and apparatus for spread spectrum clock generation is provided. Modulation of the clock signal may be accomplished with an N/N&#x2212;1 clock divider. The N/N&#x2212;1 clock divider is configured to divide the clock signal by N or N&#x2212;1, depending on the carry output signal of an accumulator circuit. The accumulator circuit is configured to provide the carry output signal in response to a modulating waveform signal. The modulating waveform signal may be a triangle wave, a sinusoidal wave, another waveform appropriate for spread-spectrum clock generation, and the like.

Apparatus and method for spread spectrum clock generator with accumulator

An analog front-end (AFE) circuit may include a correlated double sampler (CDS) with a ping-pong architecture, and a ping-pong mismatch correction circuit. The CDS employs a ping data path during ping phases, and employs a pong data path during pong phases. The ping-pong mismatch correction circuit is arranged to correct a mismatch between a gain that is associated with the ping data path and a gain that is associated with the pong data path. Further, the ping-pong mismatch correction circuit is arranged to correct a mismatch between an offset that is associated with the ping data path and an offset that is associated with the pong data path.

Apparatus and method for ping-pong mismatch correction

This invention discloses a method of increasing muscle mass comprising administering phospholipid arachidonic acid to a human in need thereof.

Use of phospholipid arachidonic acids for increasing muscle mass in humans

Techniques for DC offset cancellation are described. According to one embodiment, an amplifier has at least one output and first and second supply rails. The amplifier includes offset cancellation logic which is operable in a calibration mode to generate a first offset cancellation signal when the at least one output is coupled to a first voltage corresponding to the first supply rail, and a second offset cancellation signal when the at least one output is coupled to a second voltage corresponding to the second supply rail. The offset cancellation logic is further operable to facilitate at least partial cancellation of an offset voltage associated with the at least one output during a normal operation mode using a third offset cancellation signal which substantially corresponds to an average of the first and second offset cancellation signals.

DC offset self-calibration system for a switching amplifier

Apparatus and methods for enabling and disabling an amplifier is described. Amplifiers can be enabled and disabled for the sake of power and energy savings and reduction of dissipated heat. The circuit is based on a gain stage and threshold circuitry. A signal associated with an amplifier is introduced into the gain stage. The gain stage amplifies the signal level and provides the amplified signal level to threshold circuitry. The threshold circuitry references the amplified signal level and determines signal states. The control circuitry interprets these signal states to determine when to enable or disable an amplifier. The output of the threshold circuitry can be used to adjust the amplified signal level to oppose drift in the gain stage.

Methods and apparatus for enabling or disabling an amplifier

A differential amplifier includes first and second outputs and first and second supply rails. The differential amplifier further includes offset cancellation circuitry. The offset cancellation circuitry is operable during a calibration mode to generate an offset cancellation signal when the first and second outputs are both coupled to a voltage between the first supply rail and the second supply rail. The offset cancellation signal is for facilitating at least partial cancellation of an offset voltage associated with the first and second outputs during a normal operation mode of the differential amplifier.

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San Jose, CA, United States of America

William David Llewellyn