International Business Machines Corporation

William D Silkman

Benedicto U Messina

Matthew A Krygowski

John E Andersen

Joseph Anthony Petrosky, Jr

A directory memory system having simultaneous writing and bypass capabilities. A data output bit from a respective memory cell of a memory array is applied to a control input of a first differential amplifier, while comparison input data is applied to inputs of a second differential amplifier. The outputs of corresponding transistors of the two differential amplifiers are connected together. Current switch transistors, operated in response to a bypass select signal, supply current only to one or the other of the two differential amplifiers. The differential output signal produced across the commonly connected outputs of the two differential amplifier circuits is buffered and amplified with a push-pull output circuit.

Directory memory system having simultaneous write and comparison data

The disclosure provides a plurality of embodiments for controlling the bus paths for a line of data from any cache in a multiprocessing system (MP) to any requesting cache or I/O channel processor in the MP. The data transfers can occur in parallel among plural CPU caches, channel processors and main storage (MS) sections using crosspoint switches in a manner which utilizes the high circuit count of LSI modules without substantially utilizing the module I/O pin count to enable MP structures to contain more CPUs than could be contained with conventional bussing.

System for independent cache-to-cache transfer

A fast synonym detection and handling mechanism is disclosed for a cache directory utilizing virtual addressing in data processing systems. The cache directory is divided into 2.sup.N groups of classes, in which N is the number of cache address bits derived from a translatable part of a requested logical address. The cache address is derived from a non-translatable part of the logical address which is used to simultaneously select one class in each of the 2.sup.N groups. The selected class entries are simultaneously compared with one or more dynamic lookaside address translator (DLAT) translated absolute addresses. Compare signals, one for each class entry per DLAT absolute address, are routed to a synonym detection circuit. The detection circuit simultaneously interprets all directory compare signals and determines if a principle hit, synonym hit or a miss occurred in the cache for each request. A principle hit occurs in the group selected by the translatable part of the requested address, and a synonym hit occurs in one of the other groups. If a synonym hit is detected, the group identifier bits for the group having the hit are concatenated with the non-translatable bits used as the cache address for locating the required cache data. For a set-associative cache, set identifier bits are simultaneously generated for cache addressing.

Cache synonym detection and handling mechanism

A cache organization that enables many cache functions to overlap without extending line fetch or line castout time and without requiring a cache technology faster than the processor technology. Main storage has a data bus-out and a data bus-in, each transferring a double word (DW) in one cycle. Both busses may transfer respective DWs in opposite directions in the same cycle. The cache has a quadword (QW) write register and a QW read register, a QW being two DWs on a QW address boundary. During a line fetch (LF) of 16DWs, either the first pair of DWs, or the first DW of the LF is loaded into the QW write register, depending on whether the first DW is on a QW address boundary or not, i.e., whether the fetch request address bit 28 is even or odd, respectively. Thereafter during the LF, the even and odd DWs are formed into QWs as received from the bus-out, and the QWs are written into the cache on alternate cycles, wherein no QW cache access occurs on the other alternate cycles for the LF. Either 8 or 9 QWs occur for a LF depending on the first DW boundary alignment. For a LF with 9 QWs, a write inhibit is needed for a non-data odd DW position in the last QW to avoid destroying the first DW written in the cache. If a line castout (CO) is required from the same or a different location in the cache, the CO can proceed during the alternate non-write cycles of any LF. Any cache bypass to the processor during the LF can overlap the LF and CO. Any alternate cycles during any LF, which are not used for a CO or LF bypass, are available for processor request accesses of the cache for either DWs or QWs.

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Hopewell Junction, NY, United States of America

William D Silkman