Lsi Logic Corporation

Lsi Corporation

William D Scharf

Majid Bemanian

Gary Scott Delp

George Wayne Nation

Hong Hao

Keven Hui

Narayanan Raman

John N Fryar, Iii

Bruce L Entin

A partially manufactured semiconductor chip comprising a slice and a number of shells is a template for a communication and networking chip. The slice has a number of I/O ports, blocks, and PHYs. The hardmac PHYs are established to correspond to a high speed data transmission protocol. The interior of the template comprises logic gate arrays and configurable memory. Once particular protocols of data receipt and transmission are selected, the logic gate arrays and configurable memory can be programmed and otherwise configured to develop protocol layers for data networking and communication.

Flexible template having embedded gate array and composable memory for integrated circuits

The present invention is a method and apparatus for implementing a source synchronous interface in a platform using a Generic Source Synchronous Interface (GSSI) infrastructure. The GSSI infrastructure includes the GSSI bit slices and clock management system. The GSSI bit slice includes balanced cells and bit delay elements, and may be placed either within or close to IO buffers. The GSSI clock management system includes strategically placed frame delay elements with automatic on-chip calibration and control to satisfy various clock-data phase relationships. The GSSI methodology shows how different SSIs may be constructed by combining the common GSSI architecture with unique metal layer configurations. The GSSI architecture solves a critical challenge for platform-based design such as RapidChip&#x2122; and the like. The GSSI approach introduces a completely new way to implement various SSIs based on a common minimally diffused GSSI bit slice and clock management infrastructure. This enables one slice of a platform family to be used for many applications, removing the need to provide different slices with different diffused hard macros for different applications.

Generic method and apparatus for implementing source synchronous interface in platform ASIC

An integrated circuit (IC) and a method of manufacturing an integrated circuit suited for a particular application. In one embodiment, the IC includes: (1) at least two interfaces, (2) a programmable gate array (PGA) coupled to the at least two interfaces for communicating data therebetween and, optionally (3) a field-programmable gate array (FPGA) coupled to and configured to cooperate with the PGA to adapt the IC to a particular surrounding environment.

Integrated circuit having integrated programmable gate array and method of operating the same

An integrated circuit (IC) and a method of manufacturing an integrated circuit suited for a particular application. In one embodiment, the IC includes at least two interfaces, a field-programmable gate array (FPGA) and a programmable gate array (PGA). The FPGA has a configuration memory associated therewith and is coupled to the at least two interfaces for communicating data therebetween. The PGA is coupled to and configured to cooperate with the FPGA to adapt the IC to a particular surrounding environment.

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San Jose, CA, United States of America

William D Scharf