National Semiconductor Corporation

Cera M Gmbh

Ramtron International Corporation

Other

Micron Technology Incorporated

William D Miller

Joseph T Evans, Jr

Richard Hiram Womack

Gary L Harrington

Leo N Chapin

William H Shepherd

Thomas M Mnich

Wayne I Kinney

E J Weldon, Jr

Lawrence M Fullerton

Christopher M Bellman

Larry M Fullerton

Chris M Bellman

A non-volatile memory cell and related system utilize ferroelectric capacitors as data storage elements. Circuitry is provided for writing to a single ferroelectric capacitor storage element, as well as to dual storage elements operating inversely. The storage elements are read by use of a sense amplifier in a configuration which automatically restores the original data states, thereby eliminating the need for a subsequent restore operation. Memory systems are described which include circuitry for driving bit lines, word lines and drive lines to accomplish both the write and read operations.

Non-volatile memory circuit using ferroelectric capacitor storage element

Method for reading non-volatile ferroelectric capacitor memory cell

A method for storing data in a memory, including compressing fixed-sized pages of data, and storing the compressed pages into available smaller memory spaces on a medium if the compressed page will fit into such space, or storing the compressed pages onto available larger memory spaces on the medium, if the compressed page will not fit into the smaller space.

Data compression and decompression using memory spaces of more than one

A ferroelectric capacitor structure is designed for fabrication together with MOS devices on a semiconductor substrate. The ferroelectric capacitor includes a diffusion barrier above the surface of the substrate for preventing the materials of the ferroelectric capacitor from contaminating the substrate or MOS devices. The ferroelectric capacitor comprises a bottom electrode, a thin film ferroelectric layer and a top electrode. An interlayer dielectric is formed to cover portions of the ferroelectric thin film and provide an opening therethrough for the top electrode. A ferroelectric memory cell comprises a field effect transistor together with a ferroelectric capacitor fabricated on a semiconductor substrate. In one configuration, the ferroelectric capacitor is offset from the field effect transistor, while in another configuration, the ferroelectric capacitor is substantially above the field effect transistor to provide greater density.

Fabrication of ferroelectric capacitor and memory cell

A computer using virtual memory management employs a random-access type storage device such as a semiconductor memory for page swapping. The semiconductor memory is formatted to provide multiple partitions of varying block size, e.g., two block sizes, for compressed pages, and another block size for uncompressed original-sized pages. The data to be stored is in pages of fixed size, and these pages are compressed for storage if the compressed size fits in the block size of one of the small-block partitions in the memory. If a data page is not compressible to one of the small block sizes, it is stored uncompressed in the other full-size partition. The operating system maintains a table storing the locations of the pages in the partitions, so upon recall the page (if compressed) is retrieved from its location found using the table, decompressed and sent to the CPU. The relative number of blocks in the partitioned memory (e.g., the physical storage capacity of the memory) is set (or dynamically allocated) at the average ratio of compressible pages to uncompressible pages for the compression algorithm used. For example, an algorithm may compress 90% of the pages to either 50% or 70% of their original size, so a ratio of the number of locations in the compressed partitions of the semiconductor memory to the number of locations in the uncompressed partition is selected as 90:10. The compression mechanism operates on bytes in bit-parallel format, and uses a lookahead buffer which is compared with bytes in a window to produce 9-bit symbols. The stream of 9-bit symbols passes through an ECC generator, also operating in bit-parallel.

Solid-state RAM data storage for virtual memory computer using

A data compression and decompression method and apparatus utilizing a sliding window dictionary in combination with an adaptive dictionary. Incoming data moves through a buffer and is compared against both the sliding window dictionary and the adaptive dictionary, and matched data is replaced with a pointer to the dictionary entry. All incoming data is entered into the sliding window dictionary, but only data which satisfies certain criteria is entered into the adaptive dictionary.

High speed lossless data compression method and apparatus using

A dynamic memory device exhibits a sleep mode of operation, entered in response to a single externally-applied signal which need not be cycled. While in this sleep mode, the device does not respond to or require any of the usual DRAM control signals such a RAS, CAS, write enable, address inputs, data inputs, etc., so all of these signals may be in a quiescent state. An internal refresh counter is used to generate row addresses while in the sleep mode, and timing for the internal refresh is provided by an internal oscillator. The memory device cycles through a sequence of row addresses for refresh while in this sleep mode, using an internal refresh address counter, and this sequence may be maintained without interruption if the sleep mode is reentered within a normal refresh period after exiting the sleep mode. Thus, a sleep-exception mode of operation is provided in which normal read or write cycles can be interposed between sleep mode periods, so the overall power drain is very low but normal access is maintained at a relatively active level.

Dynamic random access memory with operational sleep mode

A random-access type storage device such as a hard disk or semiconductor memory is formatted to provide multiple partitions of varying block size. The data to be stored is in blocks of fixed size, and these blocks are compressed if the compressed size fits in the block size of a small-block partition in the storage device. If a data block is not compressible to the small block size, it is stored uncompressed in another of the partitions. The memory device also contains a table storing the locations of the blocks in the partitions, so upon recall the block is retrieved from location, decompressed (if it had been compressed), and sent to the CPU. For example, there may be two partitions, one using the block size of the original (uncompressed) data, and the other having a block size corresponding to the typical compressed size of the blocks of data (perhaps one-half the size of the original data blocks). The relative number of blocks in each partition (e.g., the physical storage capacity of each partition) is set at the average ratio of compressible blocks to uncompressible blocks for the compression algorithm used. For example, an algorithm may compress 90% of the blocks to 50% of their original size, so a ratio of the number of blocks in the compressed partition to the number of blocks in the uncompressed partition is selected as 90:10.

Storage of compressed data on random access storage devices

A method to produce thin films suitable for fabricating ferroelectric thin films. The method provides for selection of the predetermined amounts of lead, lanthanum, zirconium, and titanium precursors which are soluble in different solvents. Dissolving predetermined amounts of the precursors in their respective solvents in proportions such that hydrolyze reaction rate for each metal precursor will be approximately equal. Preferably, the reaction is performed under an inert atmosphere at from about 350 mmHg to 650 mmHg pressure. The precursors and solvents are mixed, and water is added to begin a hydrolysis reaction. After the hydrolysis the solution is heated to drive off the excess water and solvent to promote the formation of a sol-gel. The sol-gel is then applied to a thin substrate and sintered to produce the ferroelectric film.

Method for preparing PLZT, PZT and PLT sol-gels and fabricating

A ferroelectric capacitor structure is designed for fabrication together with MOS devices on a semiconductor substrate. The ferroelectric capacitor includes a diffusion barrier layer above the surface of the substrate for preventing the materials of the ferroelectric capcacitor from contaminating the substrate or MOS devices. The ferroelectric capacitor comprises a bottom electrode, a thin film ferroelectric layer and a top electrode. An interlayer dielectric is formed to cover portions of the ferroelectric thin film and provide an opening therethrough for the top electrode. A ferroelectric memory cell comprises a field effect transistor together with a ferroelectric capacitor fabricated on a semiconductor substrate. In one configuration, the ferroelectric capacitor is offset from the field effect transistor, while in another configuration, the ferroelectric capacitor is substantially above the field effect transistor to provide greater density.

Ferroelectric capacitor and memory cell including barrier and isolation

A method to produce thin films suitable for fabricating ferroelectric thin films. The method provides for selection of the predetermined amounts of lead, lanthanum, zirconium, and titanium precursors which are soluble in different solvents. Dissolving predetermined amounts of the precursors in their respective solvents in proportions such that hydrolyze reaction rate for each metal precursor will be approximately equal. The precursors and solvents are mixed, and water is added to begin a hydrolysis reaction. After the hydrolysis the solution is heated to drive off the excess water and solvent to promote the formation of a sol-gel. The sol-gel is then applied to a thin substrate and sintered to produce the ferroelectric film.

Method for preparing plzt, pzt and plt sol-gels and fabricating

A programmable interconnection circuit includes first and second ferroelectric capacitors which differentially store the programming state of the circuit. A principal application of the circuit is in the programming of cells within a gate array integrated circuit. The programmable circuit is non-volatile due to the storage of polarization state within the ferroelectric capacitors. Differential voltage states are applied to programming nodes which set the state of a cross-coupled amplifier that, in turn, drives p-channel and n-channel transistors which are connected between first and second nodes of the integrated circuit. A drive line signal applied to terminals of the ferroelectric capacitors goes between high and low voltage states to set differential polarization states into the capacitors. Following restoration of power to the integrated circuit, which includes the programmable circuit, a pulse is applied through the drive line to the ferroelectric capacitors to create differing voltages at the program nodes. These different voltages are differentially amplified to produce the required voltage states to reestablish the programmed interconnection for the circuit.

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Rio Rancho, NM, United States of America

William D Miller