Stmicroelectronics Gmbh

William D Elliott

Charles Francis Neugebauer

Thomas M Annau

David Deckys

A system includes a digital phase lock loop (PLL) constructed from an all digital circuit implementation and standard cell construction. The digital PLL includes a digital frequency synthesizer and a digital phase detector. The digital frequency synthesizer includes a digital DLL including a plurality of delay chains, each of the delay chains including at least one digitally programmable delay element for configuring the plurality of delay chains to achieve a phase lock with an input reference signal. The digital frequency synthesizer also a non-glitching MUX electrically coupled to the digital DLL for selecting a tap output from one of the at least one digitally programmable delay element to select at least one pulse glitch-free from the selected output tap, and a phase accumulator electrically coupled to the non-glitching MUX for precisely dividing a timing period of the input reference signal and for selecting a tap output from one of the at least one digitally programmable delay element to select at least one pulse at a precise point in the timing period from the output tap. The digital phase detector, is electrically coupled to the digital frequency synthesizer to compare an edge of the input reference signal to an edge of a synthesized signal to provide a digital code information representing a phase error between the edge of the input reference signal and the edge of the synthesized signal.

Digital phase lock loop

A system includes an integrated circuit device that compares the relative phase of first and second signals to a very high precision. The system includes a first input for receiving the first signal with a first edge, and a second input for receiving the second signal with a second edge. A first delay chain includes a first at least one delay element, and the first signal is delayed across the first at least one delay element, each of the first at least one delay element includes an output tap. A second delay chain includes a second at least one delay element, the second signal is delayed across the second at least one delay element, each of the second at least one delay element includes an output tap. At least one symmetrical Flip-Flop includes a first and second input electrically coupled to an output tap of each of the first and second at least one delay element, respectively, such that an output of each of the at least one Flip-Flop indicates which of the first and second edge arrived first at the respective first and second input of the at least one Flip-Flop.

System for high precision signal phase difference measurement

A system includes a signal reconstruction controller ( ) electrically coupled to at least one analog-to-digital converter (ADC) ( ) and to a phase adjustable clock source ( ). A sampling clock signal ( ) is electrically coupled from the clock source ( ) to the at least one ADC ( ). The at least one ADC ( ) samples an electronic signal according to the sampling clock signal ( ) to provide a digital representation of the electronic signal. The controller ( ) samples data from the ADC ( ) at different sampling points in the electronic signal and determines the edges ( ) of the electronic signal and the noisy samples ( ) that are away from the edges ( ) of the electronic signal. By finding the least noisy sample ( ) that is away from the edges ( ) of the electronic signal the controller ( ) adjusts the phase of a sampling signal clock ( ) to a sampling point that is the most reliable to sample the electronic signal to provide a digital representation thereof.

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Sunnyvale, CA, United States of America

William D Elliott