Synopsys, Inc.

William Chiu-Ting Shu

Jindrich Zejda

Nahmsuk Oh

Yansheng Luo

Peivand Fallah-Tehrani

Mahmoud Shahram

Alexander Gyure

Wenyuan Wang

Chi-Chong Lo

Seyed Alireza Kasnavi

Peivand Tehrani

Khalid Rahmat

Feroze P Taraporevala

Rupesh Nayak

Systems and techniques for fixing design requirement violations in a circuit design in multiple scenarios are described. During operation, a system can receive a scenario image and a multi-scenario ECO database. The scenario image can store parameter values for circuit objects in a scenario, and the multi-scenario ECO database can store a subset of parameter values for a subset of circuit objects in multiple scenarios. Next, the system can determine an engineering change order to fix one or more design requirement violations, which can involve estimating parameter values for circuit objects in multiple scenarios using parameter values stored in the scenario image and the multi-scenario ECO database.

Fixing design requirement violations in multiple multi-corner multi-mode scenarios

Some embodiments of the present invention provide techniques and systems for determining an order for visiting circuit blocks of a circuit design for fixing design requirement violations. Fixing design requirement violations by visiting circuit blocks in this order can improve performance and quality of results. During operation, a system can determine a set of equal value segments in the circuit design. In some embodiments, the system determines equal value segments for multiple corners and combines the equal value segments to obtain the set of equal value segments. Next, the system can determine an order for visiting circuit blocks of the circuit design for fixing design requirement violations based at least on the set of equal value segments. Note that circuit block pins in an equal value segment are associated with the same parameter value, and parameter values indicate an amount or degree of a design requirement violation.

Determining an order for visiting circuit blocks in a circuit design for fixing design requirement violations

Embodiments of a computer system, a method, an integrated circuit and a computer-program product (i.e., software) for use with the computer system are described. These devices and techniques may be used to perform STA for circuits that include multiple power domains. Power-domain crossing information and optionally the delay in each power domain can be propagated during the full circuit graph-based STA to accurately perform STA without enumerating all paths. Some embodiments can use a tag-based engine to track power-domain crossing(s) during graph-based STA. If a power-domain is crossed in a path, pessimism may be added to the cumulative delay at the end point of the path. For those paths that do not cross a power domain, pessimism may be removed from the cumulative delay at their end points. In some embodiments, pessimism may be removed from the cumulative delay at end points for paths that cross power domains.

Multiple-power-domain static timing analysis

One embodiment of the invention provides a system that analyzes the propagation of noise through an integrated circuit. During operation, the system obtains an input noise signal to be applied to a cell within the integrated circuit. The system then looks up parameters specifying how noise affects the cell, and then uses the parameters to determine how the input noise signal affects the cell. This can involve determining if the input noise signal will cause the cell to fail and/or determining a propagated noise signal that emanates from the cell.

Method and apparatus for detecting and analyzing the propagation of noise through an integrated circuit

One embodiment of the invention provides a system that characterizes cells within an integrated circuit. During operation, the system obtains a number of input noise signals to be applied to the cell. The system then simulates responses of the cell to each of the input noise signals, and stores a representation of the responses. This allows a subsequent analysis operation to access the stored representation to determine a response of the cell instead of having to perform a time-consuming simulation operation.

Method and apparatus for characterizing the propagation of noise through a cell in an integrated circuit

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Palo Alto, CA, United States of America

William Chiu-Ting Shu