Microsoft Technology Licensing, LLC

William Chambers Powell, Iii

James E Veres

Steven A Gabriel

George Easton Scott, Iii

John G Torborg, Jr

William Jefferson Westerinen

Michael A Toelle

Joseph W Chauvin

Kent E Griffin

Howard Good

Ming-Chieh Lee

James Morris Alkove

Dawson Yee

Alexandre Vicktorovich Grigorovitch

Kirt A Debique

Chad Magendanz

James Thomas Kajiya

Matthijs Arjan Gates

Mark L Kenworthy

Jeffrey Richard McKune

Alok Chakrabarti

Robin Speed

Om Kumar Sharma

The described embodiments relate to data security. One exemplary system includes a first component associated with data on which an action can be performed and a second component configured to perform the action on the data. The system also includes a third component configured to ascertain the action and determine, as a function of the action, at least one policy to be implemented prior to allowing the second component to access the data.

Policy engine and methods and systems for protecting data

A monitor having multiple displays within the same housing. The displays may be, for example, separate LCD panels that are placed in close proximity to one another so as to give the appearance of a single, large display. At least two of the displays may be treated by a computer connected to the monitor as a single display. A display controller divides a single frame of information that is provided by a display adapter of the computer into display information for multiple displays. By using the multiple display controller, the multiple display monitor may have more displays or panels than the number of cables linking the monitor to a computer. The special display controller also does not require a graphics card for each display. A three panel or display monitor is provided in which a central, centered work area display is framed by two side panels or displays.

Multiple display monitor

A display controller that permits more than one display to be operated by a single cable and a single display adapter. The display controller provides custom EDID information to a computer to which it is attached. The custom EDID information may include information about the single virtual display surface provided by all displays, and may include information about each of the individual monitors or displays, including the location of the individual displays in the single composite display surface. The single composite display surface may be utilized by computers that are not capable of recognizing the EDID for the multiple display system. If the computer does recognize the EDID for the multiple display system, the operating system of the computer and/or applications running on the computer may understand and utilize the heterogeneous nature of the display surface and may optimize display quality and presentation for a user.

Display controller permitting connection of multiple displays with a single video cable

In accordance with certain aspects of the present invention, an algorithm is provided that can be used to detect and track the difference between an on-host clock (i.e., &ldquo;host clock&rdquo;) and a remote clock (i.e., &ldquo;reference clock&rdquo;). As part of the algorithm, a scaling value is computed and tracked over time. The scaling value, when applied to the host clock, results in clock values that increase at substantially the same rate as the reference clock itself increases. Hence, the host clock will have been slaved to the reference clock.

Clock slaving methods and arrangements

The modification of timestamps of streams of data packets for seamless branching is disclosed. In one aspect of the invention, a computerized system has a plurality of multimedia play devices, and a multimedia read device. Each play device receives and plays data intended for that device. The multimedia read device reads a stream of packets of data, decodes the packets into data, and sends the data to a corresponding play device at appropriate times. The appropriate time is based on relative timestamps accounting for accumulated time gaps resulting from branches within the stream. The invention has applications including digital video disc (DVD) playback.

Timestamp modification for seamless branching

A method for still image compression reduces pixel and texture memory requirements in graphics rendering and other applications. The image compression method divides an image into blocks and stores a quantization index (QIndex) for each block that reflects the level of quantization applied to the block. The QIndex is an index into a table of QFactors. The method performs an invertable transform on a block to generate coefficients for spatial frequency components in the block. It then quantizes coefficients in the block by dividing them by the QFactor in the table corresponding to the QIndex for the block. The QIndex enables the compression ratio of an image to vary across blocks and within each block. A control structure associated with the image stores a pointer to each of the blocks in an image. This control structure allows each block to be accessed and decompressed independently.

Image compression method to reduce pixel and texture memory requirements in graphics applications

A gsprite engine circuit reads a display list identifying gsprite image layers to be composited for display, retrieves gsprite image data from an external memory, and transforms the gsprite data to display device coordinates. The gsprite image layers represent independently rendered graphical objects in a graphics scene. The gsprite engine can simulate the motion of the graphical objects in a sequence of display images by performing affine transformations on the gsprite image layers. The interface to the gsprite engine circuit includes the display list and gsprite header blocks. The display list enumerates the gsprites to be composited as a display image. The header blocks describe a gsprite transform, which can be an affine transform, used to transform gsprites to display device coordinates. The header blocks also provide an array of references to image blocks or 'chunks' comprising the gsprite.

Processor for controlling the display of rendered image layers and

A method for supporting image compression in a real-time graphics rendering pipeline includes sorting object geometry for a scene among image regions called chunks. The object geometry for each chunk is rendered separately, and in a serial fashion. After the object geometry is completely rendered for a given chunk, the pixel data for that chunk is compressed and stored. Each chunk of an image can be generated and stored in this manner. To assemble a display image, compressed image chunks are retrieved, decompressed, and temporarily cached. Decompressed image data in the cache is combined into a display image. The process of generating a display image with compression can be performed at real-time rates.

Image compression to reduce pixel and texture memory requirements in a

A display controller, implemented in software or hardware, maintains the primary display image visible on a computer monitor in compressed subregions or chunks. The controller emulates a conventional frame buffer by making the compressed image appear as if it has a linear address space. Most of the image is compressed and the remainder is selectively decompressed and cached to satisfy read and write requests. To display the image, the controller decompresses the display image's constituent subregions and buffers the decompressed data so that it can be scanned out to a display monitor.

Method and system for accessing and displaying a compressed display

Video encoding and decoding processes provide compression and decompression of digitized video signals representing display motion in video sequences of multiple image frames. The encoder process utilizes object- or feature-based video compression to improve the accuracy and versatility of encoding interframe motion and intraframe image features. Video information is compressed relative to objects or features of arbitrary configurations, rather than fixed, regular arrays of pixels as in conventional video compression methods. This reduces the error components and thereby improves the compression efficiency and accuracy. The decoder process decompresses the encoded video information to reconstruct the objects or features of arbitrary configurations.

Object-based video compression process employing arbitrarily-shaped

A graphics rendering chip serially renders a stream of geometric primitives to image regions called chunks. A set-up processor in the chip parses rendering commands and the stream of geometric primitives and computes edge equation parameters. A scan-convert processor receives the edge equation parameters from the set-up processor and scan converts the geometric primitives to produce pixel records and fragment records. An internal, double-buffered pixel buffer stores pixel records for fully covered pixel addresses and also stores references to fragment lists stored in a fragment buffer. A pixel engine performs hidden surface removal and controls storage of pixel and fragment records to the pixel and fragment buffers, respectively. An anti-aliasing engine resolves pixel data for one pixel buffer while the pixel engine fills the other pixel buffer with pixel data for the next chunk.

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Seattle, WA, United States of America

William Chambers Powell, Iii