Micron Technology Incorporated

William Chad Waldrop

Daniel B Penney

Vijayakrishna J Vankayala

Aaron M Schoenfeld

Vladimir Mikhalev

Kallol Mazumder

Jason M Brown

Byung Sick Moon

Ravi Kiran Kandikonda

David R Brown

Scott Eugene Smith

Gary L Howe

Liang Chen

Guy S Perry

Navya Sri Sreeram

Won Joo Yun

Ryo Fujimaki

Shingo Mitsubori

Atsuko Momma

A memory device includes a command interface configured to receive write commands from a host device. The memory device also includes an input buffer configured to buffer data from the host device. The memory device further includes a write shifter configured to receive a first write command of the write commands and to shift the first command through the write shifter. The write shifter is also configured to cause the input buffer to be disabled after a first threshold of clock cycles when the first write command has shifted through the write shifter. The write shifter is additionally configured to receive a second write command and prevent the input buffer from being re-enabled until the second write command has shifted through a second threshold of stages of the write shifter.

Synchronous input buffer control using a write shifter

Apparatuses, systems, and methods for a per-DRAM addressability (PDA) synchronizer circuit. The PDA synchronizer circuit receives a write command signal which may be synchronous to a DQS clock as part of a first PDA mode or asynchronous as part of a second PDA mode. The PDA synchronizer circuit includes a delay path which provides a first PDA signal responsive to the write command signal and a synchronizer which provides a second PDA signal responsive to the write command signal. The PDA synchronizer circuit provides a synchronized write command signal responsive to whichever of the first PDA signal or the second PDA signal was provided first. When a PDA mode is disabled, the write command signal may be passed as the synchronized write command signal.

Apparatuses and methods for a per-DRAM addressability synchronizer circuit

Systems and methods that may enable alignment of a receiver enable signal with one or more clocking signals. By aligning the receiver operations with the one or more clocking signals, a likelihood of a false or incorrect data capture may be reduced, which may improve operation of a memory system. Reducing a likelihood of incorrect data capture may increase an accuracy of a distortion correction operation of a decision feedback equalizer (DFE).

Synchronous input buffer enable for DFE operation

Methods of operating a memory device are disclosed. A method may include asserting, at a semiconductor device, an internal signal in response to receipt of a command. The method may also include holding the internal signal in an asserted state for at least a predetermined time duration upon assertion of the internal signal. Further, the method may include generating an enable signal based on the internal signal and a clock signal. Associated devices and systems are also disclosed.

Methods of reducing clock domain crossing timing violations, and related devices and systems

Systems and methods are provided that provide protection from undesired latching that may be caused by indeterminate interamble periods in an input/output data strobe (DQS) signal. Interamble compensation circuitry selectively filters out interamble states of the DQS signal to reduce provision of interamble signals to downstream components that use the DQS signal to identify data latching times.

Write interamble counter

Systems and methods are described, in which a parity error alert timing interlock is provided by first waiting for a timer to count a configured parity error pulse width value and then waiting for any in-progress memory operations to complete before deasserting a parity error alert signal that was asserted in response to the detection of a parity error in a command or address.

Methods for parity error alert timing interlock and memory devices and systems employing the same

Systems and methods described herein provide decision feedback equalizer (DFE) circuitry that includes one or more phases. The one or more phases receive bit feedback at respective inputs of the phases. The DFE circuitry also may include variable reset circuitry. The variable reset circuitry may reset voltages of the bit feedback at inputs of each of the phases. The variable reset circuitry is configured to change its reset frequency between resets.

Reset speed modulation circuitry for a decision feedback equalizer of a memory device

Memory devices receive a data signal and an accompanying data strobing signal, which informs the device that data is ready for latching. The data strobing signal enables capturing the data while the data signal transitions from a logic high to a logic low or vice versa, resulting in an indeterminate output (e.g., between 0 and 1). The indeterminate value may cause metastability in memory operations using the indeterminate output. To prevent or reduce metastability, a cascaded timing arbiter latch includes cascaded alternating NAND timing arbiters and NOR timing arbiters. In some embodiments, these logic gates are connected to transistors above and below the cascaded timing arbiters. The cascaded timing arbiters and/or transistors provide amplification on a feedback path of the latch. In other embodiments, the cascaded timing arbiters are isolated by inverters and are not connected to transistors. This embodiment reduces capacitive loading on nodes of the internal feedback path.

Metastable resistant latch

Systems and methods are provided that include an interamble data strobe (DQS) counter configured to count cycles between write operations. The interamble DQS counter includes a decision feedback equalizer (DFE) reset mask circuit configured to generate a DFE reset enable signal and a DFE reset timing generator configured to generate timing signals for the DFE reset. The systems and methods also include a DFE reset generator configured to receive the DFE reset enable signal and the timing signals from the interamble DQS counter, to use the DFE reset enable signal and the timing signals to generate DFE reset signals for a plurality of DQS phases; and to transmit the DFE reset signals to the plurality of DQS phases.

Centralized DFE reset generator for a memory device

Aspects of the present disclosure eliminating the need for a memory device to have both a shifter that shifts input pin values from an input domain into a parity domain and another shifter that shifts a decoded command from the input domain into the parity domain. A memory device can achieve this by, when parity is being performed, shifting the input from the input pins into the parity domain prior to decoding the command. Using a multiplexer, the decoder can receive the command pin portion of the shifted input when parity checking is being performed and can receive the un-shifted command pin input when parity checking is not being performed. The decoder can use the command pin portion of the shifted input to generate shifted and decoded commands or can use the un-shifted command pin input to generate decoded commands.

Reduced shifter memory system

Devices and methods for error checking transmissions include using error checking circuitry configured to receive a clock and reset. The error checking circuitry (ECC) includes an input counter configured to receive the clock and to count out multiple input clocks from the received clock. The ECC also includes a delay model configured to receive the clock and to output a delayed clock. Also, the ECC includes an output counter configured to receive the delayed clock and to count out multiple output clocks from the received delayed clock. Furthermore, the ECC includes multiple error calculation circuits arranged in parallel that each are configured to: receive data based on a respective input clock, generate an error indicator based on the received data with the error indicator indicating whether an error exists in the received data, and output the error indicator based at least in part on a respective output clock.

Parallel error calculation

Systems, methods, and devices are provided for increasing uniformity of wear in semiconductor devices due to, for example, negative-bias temperature instability (NBTI). The method may include receiving a first NBTI control signal. The method may involve receiving a second NBTI control signal based at least in part on the first NBTI control signal. The method may also involve asserting the first NBTI control signal at a clock input pin of a latch. Further, the method may include asserting the second NBTI control signal at a data input pin of the latch. The method may additionally involve toggling electrical elements downstream of the latch based at least in part on an output of the latch based on the first and second NBTI control signals to increase uniformity of wear on the electrical elements in a default low-power state during NBTI toggling mode.

Systems and methods for controlling semiconductor device wear

Systems and methods providing for a parity error synchronization based on a programmed parity latency value by delaying an activation of a command disable signal to disable internal commands such that the command disable signal activates just prior to the parity error command.

Growing community of inventors

Allen, TX, United States of America

William Chad Waldrop