Other

Boschert, Inc.

William C Voight

Arthur B Odell

An inverter (100) receives a DC voltage and generates therefrom a square wave output signal. The inverter includes an output transformer (T3) and a saturable core transformer (T4). The saturable core transformer (T4) provides base current for a first transistor (Q3) and a second transistor (Q4). The first transistor (Q3) and the second transistor (Q4) alternatively turn on and off, causing a square wave to appear across the secondary winding of the output transformer (T3). The primary winding of the output transformer is coupled to the collectors of the first and second transistors via a pair of windings (L10, L11) magnetically coupled to the saturable transformer (T4). A pair of diodes (D4, D5) are provided to prevent the output leads of primary windings of the output transformer (T3) from dropping below ground potential. In addition, a pair of saturable inductive elements (118, 120) or diodes (D8, D9 or D10, D11) are coupled between the primary windings of the output transformer (T3) and the collector windings (L10, L11) of the saturable transformer (T4) to prevent a drop in the voltage at the primary windings of the output transformer from altering the volt seconds appearing across the saturable core transformer (T4).

Inverter using current steering saturable inductors or diodes

A regulator for a blocking oscillator includes overcurrent protection and light-load operation. An error signal derived from sensing output voltages is then summed with an opposite sense ramp voltage at the input of a comparator having a high amount of hysterises. When sufficient ramp voltage is generated to cause the comparator to switch, a pulse is generated to cause the main power switch to turn off. Variations of the error voltage thus causes the ramp time to vary in a way which opposes changes in the voltage at the load.

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San Francisco, CA, United States of America

William C Voight