Sgs-thomson Microelectronics Limited

William C Slemmer

David C McClure

Mark A Lysinger

Thomas A Coker

Bahador Rastegar

James Brady

Bruce A Doyle

According to the present invention, a circuit, utilizing a minimum number of bipolar devices and current mirror scaling devices, generates a bandgap reference voltage. The bandgap voltage generated by the bandgap reference circuit is a function of a plurality of sized current mirror devices, the ratio of a first resistor to a second resistor, and the number and relative sizing of bipolar junction transistors used. The bandgap reference circuit generates a bandgap reference voltage which is suitable for use in a variety of integrated circuit devices, such as a zero power static random access memory (SRAM). If used in a zero power SRAM application, the bandgap reference voltage may be utilized to determine when the primary power source of the zero power SRAM has fallen below a predetermined voltage level and a secondary power source must be substituted for the primary power source.

Bandgap reference circuit

A direct current sum bandgap voltage comparator for detecting voltage changes in a power supply. The direct current sum bandgap voltage comparator includes a summing node, current sources connected to the summing node and the power supply, and an indicator circuit connected to the summing node. Each current source supplies a current to the summing node wherein the summing node voltage level is responsive to the currents supplied. The indicator circuit is responsive to changes in the summing node voltage level and generates at an output a logical signal at one state when the summing node voltage level is greater than a predetermined value and generates the logical signal at the output at another state when the summing node voltage level is less than the predetermined value, the predetermined value corresponding to a preselected power supply voltage.

Direct current sum bandgap voltage comparator

According to the present invention, a structure for holding broken select lines in a memory array deselected addresses the prior art problems associated with floating broken select lines, such as standby current and disruption of attached memory cells. The structure is a non-linear, high impedance device which is placed on the end of select lines so that if a select line is broken during fabrication, the non-linear, high impedance device will hold the broken end of the select line to the desired deselect voltage. Select lines which have a driver at one end only and are broken during fabrication, but have the non-linear, high impedance device on the other end, are not allowed to float. The non-linear, high impedance device is also suitable for select lines which are not broken and previously were anchored at just one end. Suitable non-linear, high impedance devices include a reverse biased diode, a weak transistor, a bulk transistor, a poly R memory cell load device, an ON or OFF TFT memory cell load device, or other transistor structures. Additionally, the use of non-linear devices, such as transistor structures, provides the advantage of a compact layout structure that is especially suitable for high density integrated circuit memory devices.

Structure for deselecting broken select lines in memory arrays

An integrated circuit memory is disclosed which has its memory array divided into blocks, or sub-arrays. Between each sub-array is placed a row line repeater which communicates the row line from the row decoder, or from a prior sub-array, into the next sub-array. The row line repeaters are controlled according to a portion of the column address so that, after the entire selected row has been energized, those row line repeaters which are not associated with the selected sub-array will de-energize the row line at their output. The row line repeaters each include a latch, so that the row line repeater which is associated with the selected sub-array will maintain the selected row line energized. Various embodiments of the row line repeater circuit are disclosed. Further control of the row line repeaters from a power-on reset circuit is also disclosed. A dummy row line is also disclosed, which emulates an actual row line so that the time at which the selected row has been fully energized is more closely known. The dummy row line thus can control the time at which the unselected row line repeaters de-energize their outputs.

Semiconductor memory with power-on reset controlled latched row line

Fuse circuitry is presented which emulates fuse blowing in a temporary manner. As an embodiment, redundant elements of an integrated circuit may be enabled and/or tested prior to laser repair through the use of non-destructive fuse circuitry which emulates fuse blowing. An integrated circuit has a plurality of addressable elements and a plurality of redundant elements, which may be used to replace defective addressable elements. Each redundant element has a non-destructive fuse circuit associated with it which may be used to enable and/or test the redundant element prior to laser repair by emulating the blowing of a fuse contained in the non-destructive fuse circuit. The non-destructive fuse circuit is comprised of a fuse connected to a control logic element, such as an inverter, wherein the control logic element is in turn controlled by a test signal. Emulation of blowing the fuse or not blowing the fuse is accomplished by the logic level of the test signal. So, rather than connecting the fuse to a power supply, the fuse is connected to the control logic element which is controlled by the test signal. Thus, non-destructive enabling and testing of a redundant element prior to laser repair may be accomplished by emulating blowing or not blowing of the fuse through the control logic element. The fuse can then be permanently blown if desired.

Integrated circuit with fuse circuitry simulating fuse blowing

A clock generator circuit for producing a clock signal while drawing reduced current drain is disclosed. The clock generator circuit includes a crystal oscillator which produces a periodic signal having a relatively small voltage swing, controlled by one or more reference voltages; the reference voltages are preferably produced by a sub-threshold biased voltage reference circuit. The small signal output of the crystal oscillator is applied to the first of a series of frequency divider stages, prior to amplification by a level shift circuit. Each divider stage includes a current switch which switches the current drawn through current divider legs to produce output signals to latches in the divider stage. Each divider stage also includes one or more current source switched latches, each controlled by current sources that are switched by the current switch. As a result, each divider stage divides the frequency of the oscillator output signal without requiring amplification of the signal, thus reducing the active current. The output of the last divider stage is applied to a level shift circuit to provide the large voltage swing clock signal.

Clock generator circuit with low current frequency divider

According to the present invention, a structure for holding broken select lines in a memory array deselected addresses the prior art problems associated with floating broken select lines, such as standby current and disruption of attached memory cells. The structure is a high impedance device which is placed on the end of select lines so that if a select line is broken during fabrication, the high impedance device will hold the broken end of the select line to the desired deselect voltage. Select lines which have a driver at one end only and are broken during fabrication, but have the high impedance device on the other end, are not allowed to float. The high impedance device is also suitable for select lines which are not broken and previously were anchored at just one end. Suitable high impedance devices include a reverse biased diode, a weak transistor, a poly R memory cell load device, and an ON or OFF TFT memory cell load device.

A push-pull output driver circuit is disclosed which includes control circuitry for controlling the gates of the driver transistors to effect precharge of the output terminal at the beginning of a cycle. Precharge is initiated at the beginning of each cycle, for example indicated by an address transition. The prior data state at the output is stored, and enables the opposing driver transistor from that which drove the stored prior data state by enabling a gated level detector with hysteresis, such as a Schmitt trigger, associated therewith. The transistor that drove the stored prior data state is disabled, thus precluding oscillations during precharge. The gated Schmitt triggers each receive the voltage of the output terminal and, when enabled, turn on a transistor which couples the output terminal to the gate of the driver transistor. The Schmitt triggers also control the precharge to terminate when the output terminal has reached an intermediate voltage, and so that oscillations are minimized as a result of the hysteresis characteristic. Connection of the output terminal to the gate of the precharging driver transistor helps to eliminate overshoot during precharge.

Precharging output driver circuit

A semiconductor memory including test circuitry for directly determining the functionality of internal circuitry. The gates of test transistors are connected to the ends of signal lines in the memory, examples of which include bit lines, row or word lines, and control signal lines. Upon entry into a special test mode, the test transistors are biased to a voltage such that the active signal, if present, will turn on the test transistor and produce a signal indicating whether or not the active signal reached the test transistor. Multiple test transistors may be used to provide additional information, including the presence of short circuits, and the operation of multiple circuits within the memory.

Testing circuitry of internal peripheral blocks in a semiconductor

Circuits and methods for generating a delay added to a clock signal which clocks an output of a first circuit into an input of a second circuit in a semiconductor device is disclosed. In a first embodiment, a delay circuit is provided for generating an output clock signal for controlling a circuit internal to an integrated circuit, such as a clocked sense amplifier in a memory device, relative to an earlier timing signal, such as a row select signal. The delay circuit is implemented by components having their design parameters, such as transistor dimensions and transistor orientation, corresponding to elements in an active portion of the circuit, such as memory cell transistors. Process variations that affect the electrical properties and the speed of the transistors in the active portion of the circuit will similarly affect the electrical properties and speed of transistors in the delay circuit, so the delay circuit can track and automatically compensate for process-induced speed variations, eliminating the need for large design time margins. Alternative embodiments are also disclosed which account for the threshold voltage drops across pass transistors in a memory array, and mimic the memory cell read current, when generating a sense amplifier clock signal.

Compensating delay element for clock generation in a memory device

A push-pull output driver including two transistors in series, one transistor having its body bias controlled by logic circuitry commanded by the driver input. The driver has a pair of transistors in series, the transistor inputs being complementary to create a push-pull amplifier. A switching transistor is controlled by the inverse of the driver input signal and acts as a switch at the pull-up transistor well-tie. When the driver input is high, the switching transistor is off allowing the well-tie to the pull-up transistor to be connected to the driver output. When the input is low, the switching transistor turns on, switching the well-tie of the pull-up transistor to ground. By controlling the body bias of the pull-up transistor in this way, the switching speed of the output driver is significantly increased. When the output driver is in a disabled tri-state mode, the series transistors, and the switching transistor, are turned off. A first deselect transistor provides a high voltage at the drain of a load transistor to force it into cutoff. A select transistor is turned off to isolate the pull-up transistor well-tie from the output node, and a second deselect transistor is switched on to connect it to ground. This embodiment isolates the well-tie from the driver output while in tri-state to prevent latch-up initiated by multiple power supply operation.

Output driver circuit with body bias control for multiple power supply

An integrated circuit having a memory, and a method of operating the same, which provides for improved test efficiency. The memory includes static random access memory cells which power up in a preferred state; the preferred state draws less standby power, and is less susceptible to noise and other undesired effects which could cause upset of the stored data state. The method of testing the memory includes writing the memory cells with the complement of the preferred data state, so that all memory cells contain the higher current state; measurement of the standby current after the writing of the complement of the preferred data state will thus measure the worst case standby current. The method of testing may also include a disturb test, where the cell under test, or a neighboring cell in an adjacent row, is repeatedly accessed; such disturbing thus performs the worst case test, since the preferred state is more stable than its complement. Circuitry for performing the inverted write-back of the stored contents is also disclosed, so that such write-back may be performed without requiring read and write operations from the external terminals of the circuit.

Semiconductor memory with inverted write-back capability and method of

A voltage level sense circuit that has temperature compensation is disclosed. The circuit includes charge-sharing capacitors in each of an input leg and a reference leg. The charge-sharing capacitors are precharged to voltages that are integral multiples of the forward bias voltage drop across the base-emitter junction of a bipolar transistor. The bipolar transistors in the input leg differ from those in the reference leg, so that the difference in base-emitter on voltages increases with temperature. The increasing difference in base-emitter on voltage compensates for the decrease in the absolute value of the base-emitter on voltage with temperature. Voltage level sensing is accomplished by sampling the input voltage with a capacitor, charge-sharing the sampled voltage with one of the precharged charge-sharing capacitors, and coupling the charge-shared result to an input of a differential amplifier comparator. The second charge-sharing capacitor, after sharing its charge with another capacitor inserted for purposes of circuit matching, is coupled to the other input of the differential amplifier, and the comparison is performed.

Temperature-compensated voltage level sense circuit

According to the present invention, a first circuit is used to detect a positive voltage transition on a signal line. A second circuit is used to detect a negative voltage transition on the signal line. Upon detecting a transition, the first circuit will drive the signal line high. The second circuit pulls the line to ground after sensing a negative voltage transition. A delay circuit determines the time period in which the first or second circuit is connected to the signal line.

Signal line pulse enhancing circuit for integrated circuits

A memory is disclosed having a plurality of memory cells in a memory array arranged in rows and columns, each of the memory cells capable of storing a logic state therein. Each pair of bit lines is associated with one of the columns. A column decoder selects a column in the array responsive to a column address. A plurality of word line drivers selects, in response to a row address, a row of memory cells for connection with their associated pair of bit lines. A plurality of row isolation circuits isolates and enables a selected group of memory cells of each row from the remainder of the row in response to a bulk write signal. Each row isolation circuit has a conduction path between its associated word line driver and the selected memory cells in the associated row. A bulk write signal is sent to each column containing the selected memory cells. A first logic state is then written into the selected memory cells in response to the bulk write signal.

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Dallas, TX, United States of America

William C Slemmer