Freescale Semiconductor,inc.

Motorola Corporation

Nxp Usa, Inc.

Rambus Inc.

Other

Cryptography Research, Inc.

Freescale Semiconductors Inc.

William C Moyer

Jeffrey William Scott

John H Arends

Michael D Fitzsimmons

John E Zolnowsky

Quyen Pho

Brett W Murdock

Jimmy Gumulja

Claude Moughanni

Richard G Collins

John J Vaglica

Gary L Whisenhunt

Lea Hwang Lee

Ravindraraj Ramaraju

Michael D Snyder

Douglas B MacGregor

Yui K Ho

Taimur Aslam

Joseph A Gutierrez

Ray Charles Marshall

Hunter Ledbetter Scales, Iii

William C Bruce

Afzal M Malik

Joseph Charles Circello

Shayan Zhang

Andrew Christopher Russell

Alistair Robertson

Zheng Xu

David S Mothersole

Gary R Morrison

Tommi M Jokinen

Michael W Cruess

Jason T Nearing

James C Holt

Michael J Rochford

William M Keshlear

James B Gullette

William D Wilson

Perry H Pelley

Gary L Miller

Kenneth R Burch

Kevin B Traylor

Troy L Cooper

Brian Christopher Kahne

Brian Geoffrey Lucas

Dan E Tamir

Brian M Millar

Richard Soja

Jay A Hartvigsen

Brian D Branson

Craig D Shaw

Michael Julio Garcia

Kelly K Taylor

Ryan D Bedwell

Terry V Hulett

Jonathan J Gamoneda

Charles W Kirtland

Imran Ahmed

Marvin A Mills, Jr

Steven L Schwartz

Prashant U Kenkare

Keith E Diefendorff

Thomas E Tkacik

David R Bearden

Anis Mahmoud Jarrar

James G Gay

James B Eifert

David B Kramer

Philip E May

Jeffrey Van Myers

Mark Maiolani

David W Chrudimsky

Kent Donald Moat

Jesse R Wilson

Raymond Brooke Essick, Iv

Donald C Anderson

Michael E Spak

Joseph Gergen

Timothy J Strauss

Qadeer A Qureshi

Anthony M Reipold

James S Golab

Lester M Crudele

Huy Nguyen

John F Pillar

James M Norris

Ezra Baruch

Jose A Lyon

James C Nash

Arnaldo R Cruz

James S Thomas

Tuongvu Van Nguyen

Sanjay Wanchoo

Michael Kardonik

Sunil P Khatri

David R Gonzales

Yaron Gold

Benjamin C Eckermann

Jim C Nash

John Kelley

A data processing system having debugging circuitry and a method for operating the data processing system is provided. In the system, a processor has a cache memory and is coupled to a system bus. An instruction is received which indicates an effective address. The instruction is executed and it is determined if the effective address results in a hit or a miss in the cache. If the effective address results in a hit, data associated with the effective address is provided from the cache to the system bus without modifying a state of the cache. The instruction allows real-time debugging circuits to be able to view the current value of one or more variables in memory that may be hidden from access due to cache hierarchy without modifying the value or impacting the current state of the cache.

Data processing system having cache memory debugging support and method therefor

A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction, performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected.

Configurable pipeline based on error detection mode in a data processing system

Each task assigned to a core can be considered an 'active' task. Sequential strobe signals of a watchdog signal can be spaced apart in time by a certain duration. The duration between strobe signals is longer than the expected duration of an active task. By knowing that all tasks being monitored are expected to execute within an expected amount of time, the duration between the strobe signals can be set to be longer than that expected amount of time. If a task has not transitioned to inactive by a next strobe, a watchdog error has occurred.

Watchdog method and device

A data processing system includes an instruction pipeline, a bus interface unit, and a cache. The instruction pipeline is configured to assert a discard signal when a speculative read request is determined to have been mispredicted. The speculative read request has a corresponding access address. The bus interface unit is configured to communicate with an external system interconnect. The cache includes a cache array and cache control circuitry. The cache control circuitry is configured to receive the discard signal from the instruction pipeline and, when the discard signal is asserted after the access address has been provided to the external system interconnect by the bus interface unit in response to a determination by the cache control circuitry that the access address missed in the cache array, selectively store the read information returned from the access address into the cache array.

Data processing system with speculative fetching

In one or more embodiments, one or more systems, method, and/or processes described herein can change/switch from a first trace mode to a second trace mode without halting a system under development and/or under test. For example, a debug/trace unit can switch a trace mode without halting a processing unit of a system under development and/or under test. For instance, a debug/trace unit can switch a trace mode that can occur on a change of flow boundary of program instructions executable by a processing unit, at a branch instruction, if a region of program instructions is entered or exited, and/or if a capacity of a buffer changes. In one or more embodiments, Nexus messages can be utilized, and trace mode switches can include switches to and/or from traditional and history traces modes.

Switching between traditional and history program trace modes without halting a processor

Task context information is transferred concurrently from a processor core to an accelerator and to a context memory. The accelerator performs an operation based on the task context information and the context memory saves the task context information. The order of transfer between the processor core is based upon a programmable indicator. During a context restore operation information is concurrently provided to data bus from both the accelerator and the processor core.

Method to communicate task context information and device therefor

Selectively performing a single cycle write operation with ECC in a data processing system

A branch instruction and a corresponding branch instruction address are received at a data processing system. A first value is received and is compared to a portion of the branch instruction address. An entry at a branch target buffer corresponding to the branch instruction is selectively allocated based on a result of the comparing.

System and method for selectively allocating entries at a branch target buffer

Configurable per-task state counters for processing cores in multi-tasking processing systems are disclosed along with related methods. In part, the disclosed embodiments include a work scheduler and a plurality of processing cores. The work scheduler assigns tasks to the processing cores, and the processing cores concurrently process multiple assigned tasks using a plurality of processing states. Further, task state counters are provided for each assigned task, and these task state counters are incremented for each cycle that the task stays within selected processing states to generate per-task state count values for the assigned tasks. These per-task state count values are reported back to the work scheduler when processing for the task ends. The work scheduler can then use one or more of the per-task state count values to adjust how new tasks are assigned to the processing cores.

Configurable per-task state counters for processing cores in multi-tasking processing systems

A data processor system includes a local memory, a processor core, and an extent monitor. The local memory stores a block of data at a task memory location that is exclusive to a particular task during a duration of time. The processor core accesses the task memory location of the local memory during the execution of the particular task, and modifies to the block of data stored in the task memory location. The extent monitor monitors a write operation the processor core to the local memory to determine a first most-extreme address of the task memory location modified by the execution of the particular task during the duration of time. The processor core also executes a write back instruction to write back to a shared memory location less than the entire block of data based upon the most-extreme address.

Access extent monitoring for data transfer reduction

Each processor of a plurality of processors is configured to execute an interrupt message instruction. A message filtering unit includes storage circuitry configured to store captured identifier information from each processor. In response to a processor of the plurality of processors executing an interrupt message instruction, the processor is configured to provide a message type and a message payload to the message filtering unit. The message filtering unit is configured to use the captured identifier information to determine a recipient processor indicated by the message payload and, in response thereto, provides an interrupt request indicated by the message type to the recipient processor.

Message filtering in a data processing system

A data processing system includes a plurality of processors, each processor configured to execute instructions, including a message send instruction, and a message filtering unit. The message filtering system is configured to receive messages from one or more of the plurality of processors in response to execution of message send instructions, each message indicating a message type and a message payload. The message filtering unit is configured to determined, for each received message, a recipient processor indicated by the message payload. The message filtering system is further configured to, in response to receiving, within a predetermined interval of time, at least two messages having a same recipient processor and indicating a same message type, delivering a single interrupt request indicated by the same message type to the same recipient processor, wherein the single interrupt request is representative of the at least two messages.

A data processing system () includes a main list () of tasks, main scheduling scheme, a starvation list () of tasks, and a secondary scheduling scheme. A method identifies tasks in the main list that are potentially-starving tasks and places the potentially-starving tasks in the starvation list. A starvation monitor () controls starvation of tasks in the system by determining when to use the secondary scheduling scheme to schedule, for execution on a CPU (), a highest priority task in the starvation list prior to scheduling, pursuant to the main scheduling scheme, other tasks in the main list. The starvation monitor determines a number of times that a task in the main list is pre-empted, by other tasks in the main list, from being scheduled for execution on the CPU. A counter () is incremented each occasion that any task not in the starvation list is executed on the CPU.

Starvation control in a data processing system

A multi-core processing system includes a first processing core, a second processing core, a task manager coupled to the first and second processing cores. The task manager is operable to receive context information of a task from the first processing core and provide the context information to the second processing core. The second processing core continues executing the task using the context information.

Multi-core system performing packet processing with context switching

Growing community of inventors

Dripping Springs, TX, United States of America

William C Moyer