Vlsi Technology, Inc.

Other

Vlsi Technologies, Inc.

William C Martin

Timothy J Powers

Habib Golnabi

The present invention is directed to providing a storage device, such as a content addressable memory, which enables multiple matches to be simply and efficiently examined during a multiple match cycle, regardless of the size of the storage device. For example, where two matched entries in a content addressable memory correspond to a search address, exemplary embodiments reduce the task of examining the locations of these matches to processing only two matched addresses as opposed to having to match all entries of the content addressable memory. By providing an efficient access to multiple matched entries of a memory, the multiple matches can actually be used in an ordered manner to access different branches of a secondary memory. The use of a relatively simple control scheme enables the control logic to be implemented on a single integrated circuit chip with the memory device itself (e.g., a content addressable memory). Moreover, in contrast to conventional content addressable memories, exemplary embodiments of the present invention enable the user to reset an original multiple matched condition, thereby allowing the user to perform several examinations of the data/address. Thus, if an error occurs during processing of multiple matches, the user can easily restart the examination process.

Method and apparatus for reading multiple matched addresses

The present invention is directed to methods and circuits for testing open collector or open drain output pads. In a preferred embodiment, the open collector or open drain outputs are hard driven to both their normal low and high level logic states during a test mode of operation. By actively driving open collector or open drain output pads to both their active and their inactive states, the existence of a stable output at any given sample time is guaranteed during a functionality test. The need to accurately estimate time delays associated with RC loads of external circuitry and the need to precisely strobe an open collector or open drain output following transition to an inactive, disabled state are therefore eliminated. Further, control signal inputs associated with a high impedance condition of open collector or open drain output pads can be directly examined at the circuit output using appropriate test logic.

Methods and circuits for testing open collectors and open drains

A method and apparatus for testing the functionality of a circuit are disclosed which reduce the number of vectors required to simulate and test cells having, for example, similar functions. By using a number of vectors which is independent of the number of cells or blocks in the circuit, the need for multiple test modes is reduced such that the time and cost associated with a functionality test can be reduced.

Method to reduce test vectors/test time in devices using equivalent

Circuitry within a device provides an output signal to an output pad of the device. One of a plurality of current levels is selected. When a first current level is selected, the circuitry generates only a first amount of current to maintain the output signal on the output pad. When a second current level is selected, the circuitry, in addition to the first amount of current, generates a second amount of current to maintain the output signal on the output pad. The first current level may be used in a test mode. In this way high current switching noise can be eliminated during testing. The second current level may then be used in a normal operating mode.

Circuit which reduces noise caused by high current outputs

An electronic device is reset using a reset line internal to the electronic device. The electronic device includes internal logic circuitry which performs logic operations. An internal logic power signal input to the electronic device is connected to an internal logic power signal line. The internal logic power signal line is used to deliver an internal logic power signal to the internal logic circuitry. The electronic device also includes a plurality of outputs. A plurality of output drivers buffer output signals generated by the internal logic circuitry. The output drivers place the output signals on the plurality of outputs. The electronic device additionally includes an output power signal input connected to an output power signal line. The output power signal line is used to deliver an output power signal from the output power signal input to the output drivers. A reset line, connected to the output power signal line and to the internal logic circuitry, is used to reset the internal logic circuitry. A reset cycle is begun by placing the internal logic power signal on the internal logic power signal line while placing a ground signal on the output power signal line. The reset cycle is completed by placing the output power signal on the output power signal line.

Provision of circuit reset without a dedicated I/O pin

A method and apparatus are disclosed for storing and accessing information of both asynchronous and synchronous devices using, for example, pointers having grey code counters which reduce code conversion logic and which are less susceptible to clock glitches, such as improper clock pulses due to internal circuit timing errors. Because the devices are less clock dependent, they do not require the imposition of critical paths during the placement and routing of a circuit layout. Further, fast and reliable accessing of information stored in memory devices can be achieved by multiplexing output bits addressed, for example, via the aforementioned grey code pointers.

Growing community of inventors

Carrollton, TX, United States of America

William C Martin