Texas Instruments Corporation

William C Loftin

Philip Leland Hower

John Lin

Tony Thanh Phan

Joe R Trogolo

William F Kyser, Jr

Ming-Yeh Chuang

Martin B Mollat

Scott Kelly Montgomery

The present invention provides an integrated circuit and a method of manufacture therefore therefor. The integrated circuit (), in one embodiment without limitation, includes a dielectric layer () located over a wafer substrate (), and a semiconductor substrate () located over the dielectric layer (), the semiconductor substrate () having one or more transistor devices () located therein or thereon. The integrated circuit () may further include an interconnect () extending entirely through the semiconductor substrate () and the dielectric layer (), thereby electrically contacting the wafer substrate ().

Integrated circuit having a top side wafer contact and a method of manufacture therefor

The present invention provides an integrated circuit and a method of manufacture therefore. The integrated circuit (), in one embodiment without limitation, includes a dielectric layer () located over a wafer substrate (), and a semiconductor substrate () located over the dielectric layer (), the semiconductor substrate () having one or more transistor devices () located therein or thereon. The integrated circuit () may further include an interconnect () extending entirely through the semiconductor substrate () and the dielectric layer (), thereby electrically contacting the wafer substrate ().

The present invention provides an integrated circuit and a method of manufacture therefor. The integrated circuit (), in one embodiment without limitation, includes a dielectric layer () located over a wafer substrate (), and a semiconductor substrate () located over the dielectric layer (), the semiconductor substrate () having one or more transistor devices () located therein or thereon. The integrated circuit () may further include an interconnect () extending entirely through the semiconductor substrate () and the dielectric layer (), thereby electrically contacting the wafer substrate (), and one or more isolation structures () extending entirely through the semiconductor substrate () to the dielectric layer ().

Integrated circuit having a transistor level top side wafer contact and a method of manufacture therefor

An interfacial oxide layer () is formed in the emitter regions of the NPN transistor () and the PNP transistor (). Fluorine is selectively introduced into the polysilicon emitter region of the NPN transistor () to reduce the 1/f noise in the NPN transistor.

Reduce 1/f noise in NPN transistors without degrading the properties of PNP transistors in integrated circuit technologies

The present invention provides a diodethat includes a substratedoped with a first type dopant and a double implanted guard ringlocated within the substrate and doped with a second type dopant opposite the first type dopant and having a first doped profile regionand a second doped profile region. The present invention also includes a method of manufacturing this diode and an integrated circuit that utilizes this diodewithin a CMOS and bipolar transistor integrated circuit

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Plano, TX, United States of America

William C Loftin