International Business Machines Corporation

William C Leipold

Edward W Conrad

Orest Bula

Mark Alan Lavin

Daniel Nelson Maynard

Timothy G Dunham

Daniel C Cole

David L DeMaris

Howard Smith Landis

James Allan Bruce

Ezra D B Hall

Bette L Bergman Reuter

Maharaj Mukherjee

John Maxwell Cohn

Michael Straight Hibbs

Michael E Scaman

Shi Zhong

Joshua J Krueger

Peter Anton Habitz

Paul Steven Zuchowski

Robert J Allen

Ivan L Wemple

David C Reynolds

Brian Douglas Pfeifer

Mitchell R DeHond

Reginald B Wilcox, Jr

Edward J Nowak

David Michael Fried

Gary S Ditlow

Donald J Samuels

Ralph James Williams

Daria Rose Dooling

Archibald John Allen

Daniel J Nickel

Eric M Coker

Stephen D Thomas

Cheryl A Hoffman

Betty L Bergman Reuter

Kathleen McGroddy

A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.

System and method for testing pattern sensitive algorithms for semiconductor design

An interconnect structure, method of fabricating the interconnect structure and method of designing the interconnect structure for use in semiconductor devices. The interconnect structure includes a damascene metal wire having a pattern of dielectric filled holes.

Shapes-based migration of aluminum designs to copper damascene

A computer program product for generating test patterns for a pattern sensitive algorithm. The program product includes code for extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.

Testing pattern sensitive algorithms for semiconductor design

The invention provides a method for providing an integrated circuit () having a substantially uniform density between parts (and) of the IC that are non-orthogonally angled. In particular, the invention provides fill tiling patterns () oriented substantially parallel to electrical structure regardless of their angle. A method of electrical analysis based on this provision is also provided as is a related program product.

IC tiling pattern method, IC so formed and analysis method

A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.

Physical design characterization system

Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region. The invention similarly transforms shapes in the defect region window into defect vectors by finding intersections between basis patterns and the shapes in the defect region. Then, the invention can easily find feature vectors that are similar to the defect vector using, for example, representative feature vectors from the index of feature vectors. Then, the similarities and differences between the defect vectors and the feature vectors can be analyzed.

System for search and analysis of systematic defects in integrated circuits

An automated system for analyzing mask defects in a semiconductor manufacturing process is presented. This system combines results from an inspection tool and design layout data from a design data repository corresponding to each mask layer being inspected with a computer program and a predetermined rule set to determine when a defect on a given mask layer has occurred. Mask inspection results include the presence, location and type (clear or opaque) of defects. Ultimately, a determination is made as to whether to scrap, repair or accept a given mask based on whether the defect would be likely to cause product failure. Application of the defect inspection data to the design layout data for each mask layer being inspected prevents otherwise acceptable wafer masks from being scrapped when the identified defects are not in critical areas of the mask.

Mask defect analysis system

A method of synthesizing layout patterns to test an optical proximity correction algorithm. The method comprises the steps of: embodying Walsh patterns in a set of Walsh pattern matrices; processing groups of matrices from the set of Walsh pattern matrices to form a set of test matrices; mapping the set of test matrices to a test pattern set.

method for generating a set of test patterns for an optical proximity correction algorithm

Disclosed is a method of locating systematic defects in integrated circuits. Extracting and index processing of a circuit design and feature searching are performed. During extracting and index processing, a window grid for the circuit design is established and basis patterns are merged with shapes within each. Shapes in each window are transformed into feature vectors by finding intersections between basis patterns and shapes. Feature vectors are clustered to produce an index of feature vectors. During feature searching, a defect region window of the circuit layout is identified and basis patterns are merged with shapes in the defect region window. Shapes in the defect region window are transformed into defect vectors by finding intersections between basis patterns and shapes. Feature vectors similar to the defect vector are found using representative feature vectors from the index of feature vectors. Similarities and differences between defect vectors and feature vectors are analyzed.

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Enosburg Falls, VT, United States of America

William C Leipold