International Business Machines Corporation

William C Brantley, Jr

Vern A Norton

Gregory Francis Pfister

Kevin Patrick McAuliffe

Joseph Weiss

Harold S Stone

Rory D Jackson

John H Anthony

Wayne S Groh

A combining switch that reduces memory accesses, synchronizes parallel processors and is easy to implement, is achieved by configuring a plurality of parallel processing nodes in a ring arrangement and by implementing a synchronizing instruction for the switch that facilitates, rather than inhibits, parallel processing. According to the preferred embodiment of the invention the ring is a token ring and the synchronizing instruction is a Fetch-and-Add instruction.

Combining switch for reducing accesses to memory and for synchronizing

Packet switch protocol and circuitry for implementing it are disclosed. According to this protocol, a message transmitter of a first node in the network may send data through a data transmission link at a predetermined rate until it is signalled, via a control signal generated by a message receiver in a second node, to suspend its transmissions. The message transmitter may also be signalled to resume transmitting data. The message receiver includes a buffer memory in which messages are temporarily stored if their selected path is blocked as they pass through the network. When the amount of available space in the buffer is less than a preprogrammed threshold value, the message receiver generates the control signal to suspend message transmission. This threshold value leaves sufficient space in the buffer to store any data which may be in the pipeline between the transmitter and the receiver. When the amount of available space rises above this threshold, the message receiver indicates to the transmitter to resume transmission. A message spanning an interface during transmission may be suspended without losing spatial contiguousness. The message transmitter also transmits a signal which marks the last portion of a message. This signal is stored in the buffer with the message data and is used to delimit messages in the buffer, allowing multiple messages to be stored in one buffer without extra delimiting values.

System for implementing to a packet switch protocol for a multinode data

A multiprocessing system is presented having a plurality of processing nodes interconnected together by a communication network, each processing node including a processor, responsive to user software running on the system, and an associated memory module, and capable under user control of dynamically partitioning each memory module into a global storage efficiently accessible by a number of processors connected to the network, and local storage efficiently accessible by its associated processor.

Multiprocessing system having nodes containing a processor and an

A method and apparatus for marking data that is temporarily cacheable to facilitate the efficient management of said data. A bit in the segment and/or page descriptor of the data called the marked data bit (MDB) is generated by the compiler and included in a request for data from memory by the processor in the form of a memory address and will be stored in the cache directory at a location related to the particular line of data involved. The bit is passed to the cache together with the associated real address after address translation (in the case of a real cache). when the cache controls load the address of the data in the directory it is also stored the marked data bit (MDB) in the directory with the address. When the cacheability of the temporarily cacheable data changes from cacheable to non-cacheable, a single instruction is issued to cause the cache to invalidate all marked data. When an 'invalidate marked data' instruction is received, the cache controls sweep through the entire cache directory and invalidate any cache line which has the 'marked data bit' set in a single pass. An extension of the invention involves using a multi-bit field rather than a single bit to provide a more versatile control of the temporary cacheability of data.

Method and apparatus for efficiently handling temporarily cacheable data

A multiprocessing system is presented for dynamically partitioning a storage module into a global storage efficiently accessible by a number of processors connected to a network, and local storage efficiently accessible by individual processors, including the interleaving of storage references output by a processor, under the control of that processor, and dynamically directing the storage references to first or second portions of the storage module.

Growing community of inventors

Mount Kisco, NY, United States of America

William C Brantley, Jr