Advanced Micro Devices Corporation

Ati Technologies Ulc

William C Brantley

David Andrew Roberts

Greg Sadowski

Michael J Schulte

Kevin Y Cheng

Sriram Sundaram

Stephen Kushnir

Brent Kelley

A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.

Multi-die system performance optimization

A hardware context manager in a field-programmable gate array (FPGA) device includes configuration logic configured to program one or more programming regions in the FPGA device based on configuration data for implementing a target configuration of the one or more programming regions. Context management logic in the hardware context manager is coupled with the configuration logic and saves a first context corresponding to the target configuration by retrieving first state information from the set of one or more programming regions, where the first state information is generated based on the target configuration, and storing the retrieved first state information in a context memory. The context management logic restores the first context by transferring the first state information from the context memory to the one or more programming regions, and causing the configuration logic to program the one or more programming regions based on the configuration data.

High performance context switching for virtualized FPGA accelerators

A processor surrogate () is adapted for use in a processing node (S) of a multiprocessor data processing system () having a plurality of processing nodes (P, S) coupled together and to a plurality of input/output devices () using corresponding communication links. The processor surrogate () includes a first port () comprising a first set of integrated circuit terminals adapted to be coupled to a first external communication link () for coupling (P) of the plurality of processing nodes (), a second port () comprising a second set of integrated circuit terminals adapted to be coupled to a second external communication link () for coupling to one () of the plurality of input/output devices (), and an interconnection circuit () coupled between the first port () and the second port ().

Processor surrogate for use in multiprocessor systems and multiprocessor system using same

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Austin, TX, United States of America

William C Brantley