Xilinx, Inc.

Northern Microdesign, Inc.

Iowa State University Research Foundation Inc

Nonvolatile Electronics, Incorporated

William C Black

Charles Walter Boecker

Eric Douglas Groen

Scott Alan Irwin

Bodhisattva Das

Marwan M Hassoun

Joseph Neil Kryzak

Jerry Chuang

Timothy W Markison

Aaron Hoelscher

Matthew Shafer

Theodore M Hermann

Moises Emanuel Robinson

Michael J Gaboury

Andrew G Jenkins

Normand T Lemay, Jr

Yiqin Chen

Lin Wu

Xiaoyu Xi

Ruili (Linda) Zhang

Edward K F Lee

Scott A Irwin

Joseph N Kryzak

Aaron J Hoelscher

A method of communication over a composite cable having a plurality of conductors, the method including placing an inductive coupler around the composite cable, coupling the composite cable to a signal input or output using the inductive coupler around the composite cable to communicate a signal to or from the composite cable, wherein the signal is communicated across the composite cable from a first location to a second location, wherein the inductive coupler is at one of the first location and the second location.

Communication using multiple conductor cable

A power line carrier modem is configured for coupling to AC power lines. The power line carrier modem includes a processor, an output from the processor, a plurality of inputs to the processor, and a directional coupler operatively connected to the output, the plurality of inputs, and the AC power lines. The power line carrier modem may further include a digital-to-analog-converter operatively connected to the output from the processor. The output from the processor may be an output bus. The power line carrier modem further includes an analog-to-digital-converter operatively connected to the plurality of inputs to the processor. The power line carrier modem may be configured to perform Vector Network Analysis functions. The power line carrier modem may be configured to indicate PLC modem transmit frequencies being reflected from the AC power lines or the line coupler. The transmitter functions may be implemented in software by the processor to provide a transmit output on the output line. Receiver functions may also be implemented in software by the processor.

Power line device with directional coupler

A method for spread-spectrum communication includes forming a complex valued chipping sequence and then using the complex valued chipping sequence to spread or despread data. According to another method, a direct sequence spread spectrum (DSSS) radio performs the steps of receiving a radio-frequency signal and then identifying frequencies within the radio-frequency signal which are associated with noise sources. The DSSS radio then self-adjusts to reduce effects of the noise sources or to reduce interference created by the radio upon other communication channels.

Spread spectrum communications using complex chip sequences

Communication is provided which includes receiving a transmitted radio signal at a powerline wherein the powerline functions as a receiving antenna for the wirelessly transmitted radio signal. The powerline is coupled to an input of a radio receiver using a coupler to communicate the radio signal to the radio receiver. For calibration purposes a second antenna not coupled to powerline may be used. A method for powerline communication across transformers, open circuit breakers, and other devices is also provided. In addition, a method of monitoring a device connected to a powerline is provided.

Use of powerlines for transmission of high frequency signals

A method and apparatus are provided that allow exploitation of the common mode characteristics of a differential transmission network to provide an additional data signal. Signal represents either a binary signal or a multi-valued signal to allow signaling of one or more bits of information. The signaling occurs through the variation of the common mode voltage in transmitters and is detected using differential receiver. One embodiment is presented that achieves signaling of an extended run length data sequence to allow continued transmitter/receiver synchronization throughout the transmission of the sequence. In an alternate embodiment, a separate data path is provided to signal the extended run length sequence when a common mode signaling path is not available.

Method and apparatus for signaling characteristics of a transmitted signal

A high data rate transceiver for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream. The transceiver includes a coarse loop of a phase-locked loop that selectively provides a clock having accuracy that is within a specified amount. In a sample mode of operation, only the coarse loop PLL is coupled to provide an error signal from which an oscillation signal and clock may be derived. In a second mode (lock) of operation, the transceiver may lock to the received serial data stream by coupling the fine loop PLL to provide an adjusted error signal. In a third mode of operation, (automatic) the transceiver initially performs coarse loop calibration by de-coupling the fine loop PLL and coupling the coarse loop PLL until a steady state has been reached.

PMA RX in coarse loop for high speed sampling

A device and a method for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream and for providing the recovered clock to a circuit portion, for example, a portion of a field programmable gate array fabric, to enable the circuit portion to use either a reference clock or the recovered clock for subsequent processing. The invention specifically allows for different circuitry portions to utilize different clocks, including different recovered clocks, for corresponding functions that are being performed. Applications for the present invention are many but include multi-gigabit transceiver, switching devices, and protocol translation devices. More generally, the device and method provide for application specific clock references to be utilized in order to minimize or eliminate timing mismatch in serial data processing.

MGT/FPGA clock management system

An analog front-end having built-in equalization includes a control module and a tunable gain stage. The control module is operably coupled to provide a frequency response setting based on a channel response of a channel providing high-speed serial data to the analog front-end. The tunable gain stage includes a frequency dependent load and an amplifier input section. The frequency dependent load is adjusted based on the frequency response setting. The amplifier input section is operably coupled to the frequency dependent load and receives the high-speed serial data. In conjunction with the frequency dependent load, the amplifier input section amplifies and equalizes the high-speed serial data to produce an amplified and equalized serial data.

Analog front-end having built-in equalization and applications thereof

A distributed buffering system includes at least one input buffer, at least one serializing module, a at least one deserializing module, at least one output buffer, and a programmable logic device. The input buffer is operably coupled to store at least one data block of incoming data. The serializing module serializes the data block as it is retrieved from the input buffer to produce a serial stream of data. The programmable logic device receives the serial stream of data and distributes it to one or more of the at least one deserializing modules. The at least one deserializing module converts the serial stream back into the data block. The recaptured data block is then provided to the corresponding output buffer, which stores the recaptured data.

Method and apparatus for controlling a distributed buffering system having configurable circuitry

Method and apparatus for configuring a programmable logic device to perform testing on a signal channel is described. Configurable logic of the programmable logic device is configured for a test mode. Configurable interconnects are configured for communication from or to the configurable logic to or from transceivers coupled to the configurable input/output interconnect to communicate test signals.

Communication signal testing with a programmable logic device

A method and apparatus are provided that allow exploitation of the common mode characteristics of a differential transmission network to provide an additional data signal. Signal (MODE) represents either a binary signal or a multi-valued signal to allow signaling of one or more bits of information. The signaling occurs through the variation of the common mode voltage in transmitters (and) and is detected using differential receiver (). One embodiment is presented that achieves signaling of an extended run length data sequence to allow continued transmitter/receiver synchronization throughout the transmission of the sequence. In an alternate embodiment, a separate data path is provided to signal the extended run length sequence when a common mode signaling path is not available.

A device and a method for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream. A transceiver includes a coarse loop of a phase-locked loop that selectively provides a clock having accuracy that is within a specified amount. In a sample mode of operation, only the coarse loop PLL is coupled to provide an error signal from which an oscillation signal and clock may be derived. In a second mode (lock) of operation, the transceiver may lock to the received serial data stream by coupling the fine loop PLL to provide an adjusted error signal. In a third mode of operation, (automatic) the transceiver initially performs coarse loop calibration by de-coupling the fine loop PLL and coupling the coarse loop PLL until a steady state has been reached.

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Ames, IA, United States of America

William C Black