Qualcomm Incorporated

Motorola Corporation

Analog Devices,inc.

Other

Intel Corporation

Enverus, Inc.

William C Anderson

Lucian Codrescu

Erich Plondke

Muhammad Ahmed

Suresh Kumar Venkumahanti

Xufeng Chen

Louis Achille Giannini

Manojkumar Pyla

Thomas Tomazin

Sujat Jamil

Charles P Roth

Ravi P Singh

Ajay Naini

John H Edmondson

Juan Guillermo Revilla

Jose Fridman

Marc M Hoffman

Kayla L Chalmers

David B Witt

Michael J Allen

Keith E Diefendorff

Lawrence A Booth

Phillip M Jones

Christopher E Koob

L Rodney Goke

Ravi Kolagotla

Shankar Krithivasan

Ryo Inoue

Hebbalalu S Ramagopal

Thomas J Tomazin

Robert Allan Lester

Moinul Syed

Elie I Haddad

Meltin Bell

Russell L Rivin

Taylor Simpson

Chuan-Chang Hung

Donald Robert Padgett

Lisa J Craft

Larry Yiucham Kan

Donald L Strange-Boston

Justin Lee Shivers

William Sidney Vanderland

James Monaco

De-Lei Lee

Erich James Plondke

Russel Rivin

Michael Allen

A method includes receiving ticket and invoice data. The method further includes comparing the ticket and invoice data to rules to identify anomalies. The method further includes generating a graphical user interface displaying information related to the anomalies and selectable options to assign the anomalies to user accounts. The method further includes, in response to receiving a selection of an option to assign a particular anomaly to a user account, storing data assigning the particular anomaly to the user account. The method further includes, in response to receiving a request to access the user account, generating a graphical user interface displaying information related to the particular anomaly.

Forensics system

A processor device includes a memory and a sequencer that is responsive to the memory. The sequencer supports very long instruction word (VLIW) type instructions and at least one VLIW instruction packet uses a number of operands during execution, The processor device further includes a plurality of instruction execution units responsive to the sequencer and a plurality of register files. Each of the plurality of register files includes a plurality of registers and the plurality of register files are coupled to the plurality of instruction execution units. Further, each of the plurality of register flies includes a number of data read ports and the number of data read ports of each of the plurality of register files is less than the number of operands used by the at least one VLIW instruction packet.

Register files for a digital signal processor operating in an interleaved multi-threaded environment

A multithreaded processor device is disclosed and includes a plurality of execution units to execute a plurality of program threads and includes a global low power detection circuit. The global low power detection circuit includes an input that is responsive to each of the plurality of program threads. The input indicates an execution activity level for each of the plurality of program threads. The global low power detection circuit further comprises logic to evaluate the activity level of each of the plurality of program threads. The logic provides a power level signal. Additionally, the global low power detection circuit includes an output that is responsive to the power level signal. The output is coupled to one or more global resources within the multithreaded processor and the output selectively controls an amount of power provided to the one or more global resources.

System and method of controlling power in a multi-threaded processor

A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer supports very long instruction word (VLIW) type instructions and at least one VLIW instruction packet uses a number of operands during execution. The processor device further includes a plurality of instruction execution units responsive to the sequencer and a plurality of register files. Each of the plurality of register files includes a plurality of registers and the plurality of register files are coupled to the plurality of instruction execution units. Further, each of the plurality of register files includes a number of data read ports and the number of data read ports of each of the plurality of register files is less than the number of operands used by the at least one VLIW instruction packet.

Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Trusted and untrusted debugging operational control occurs in operating a core processor associated with the digital signal processor. A debugging process within a debugging mechanism associates with the core processor. The core processor process determines the origin of debugging control as trusted debugging control or untrusted debugging control. In the event of trusted debugging control, the core processor process provides to the trusted debugging control a first set of features and privileges. Alternatively, in the event that debugging control is untrusted debugging control, the core processor process provides the untrusted debugging control a second restricted set of features and privileges, all for maintaining security and proper operation of the core processor process.

Method and system for trusted/untrusted digital signal processor debugging operations

Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Inter-thread trace alignment with execution trace processing includes recording timing data relating to a common predetermined event. Such an event may be the number of cycles since a last thread initiated execution tracing or the number of cycles since all threads terminated execution tracing. The number of cycles at which a thread initiates execution tracing is referenced to the common predetermined event for maintaining the timing of execution tracing. The data relating to the common predetermined event is then updated to associate with the time at which the thread initiated execution tracing. The result is to permit aligning the timing data associated with all threads. Interrelated records permit reconstructing interdependent execution tracing information for threads operating in the multi-threaded processor, as well as synchronizing timing data for all operating threads.

Inter-thread trace alignment method and system for a multi-threaded processor

Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Stuffing instructions in a processing pipeline of a multi-threaded digital signal processor provides for operating a core processor process and a debugging process within a debugging mechanism. Writing a stuff instruction into a debugging process registry and a stuff command in a debugging process command register provides for identifying a predetermined thread of the multi-threaded digital signal processor in which to execute the stuff instruction. The instruction stuffing process issues a debugging process control resume command during a predetermined stage of executing on the predetermined thread and directs the core processor to perform the stuff instruction during the debugging process. The core processor may then execute the stuffed instruction in association with the core processor process and the debugging process.

Method and system for instruction stuffing operations during non-intrusive digital signal processor debugging

A method and system provide processing instructions in a multi-threaded process including the use of breakpoint instructions for generating debugging event(s). A debugging event is generated in response to the execution of breakpoint instructions and executes debugging instructions in response to the debugging event. The debugging instructions debug processing instructions in the multi-threaded processor by transitioning at least one or more threads into a debugging mode. A debugging return is generated for reporting the executing debugging instructions in the subset of the threads of the multi-threaded processor.

Non-intrusive, thread-selective, debugging method and system for a multi-thread digital signal processor

Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. The method and system improve software instruction debugging operations by capturing real-time information relating to software execution flow and include and instructions and circuitry for operating a core processor process within a core processor. A non-intrusive debugging process operates within a debugging mechanism of a digital signal processor. Non-intrusively monitoring in real time predetermined aspects of software execution occurs with the core processing process and occurs in real-time on the processor. An embedded trace macrocell records selectable aspects of the non-intrusively monitored software execution and generates at least one breakpoint in response to events arising within the selectable aspects of the non-intrusively monitored software execution. The present disclosure controls aspects of the non-intrusive debugging process in response to at least one breakpoint.

Embedded trace macrocell for enhanced digital signal processor debugging operations

A multi-threaded processor is disclosed that includes a sequencer adapted to provide instructions associated with one or more threads of a multi-threaded processor. The sequencer includes an interrupt controller adapted to receive one or more interrupts and to selectively allow a first thread of the one or more threads to service at least one interrupt. The interrupt controller includes logic to preclude a second thread of the one or more threads from responding to the at least one interrupt.

Shared interrupt controller for a multi-threaded processor

Techniques for processing transmissions in a communications (e.g., CDMA) system. An aspect of the disclosed subject matter includes a method for processing instructions on a multithreaded processor. The multithreaded processor processes a plurality of threads via a plurality of processor pipelines. The method includes the step determining the operating frequency, F, at which the multithreaded processor operates. Then, the method determines a variable thread switch timeout state for triggering the switching of the processing among the plurality of active threads. The variable thread switch timeout state varies so that each of the plurality of active threads operates at a frequency of an allocated portion of the frequency, F. The allocated portion at which the active threads operate is determined at least in part in order to optimize the operation of the multithreaded processor. The method further switches the processing from a first one of the active threads to a next one of the active threads upon the occurrence of the variable thread switch timeout state.

Method and system for variable thread allocation and switching in a multithreaded processor

A multithreaded processor device is disclosed and includes a processor that is configured to execute a plurality of executable program threads and a mode control register. The mode control register includes a first data field to control a first execution mode of a first of the plurality of executable program threads and a second data field to control a second execution mode of a second of the plurality of executable program threads. In a particular embodiment, the first execution mode is a run mode and the second execution mode is a low power mode.

Controlling execution mode of program threads by applying a mask to a control register in a multi-threaded processor

A multithreaded processor device is disclosed and includes a first program thread and second program thread. The second program thread is execution linked to the first program thread in a lock step manner. As such, when the first program thread experiences a stall event, the second program thread is instructed to perform a no operation instruction in order to keep the second program thread execution linked to the first program thread. Also, the second program thread performs a no operation instruction during each clock cycle that the first program thread is stalled due to the stall event. When the first program thread performs a first successful operation after the stall event, the second program thread restarts normal execution.

System and method of executing program threads in a multi-threaded processor

Techniques for the design and use of a digital signal processor, including processing transmissions in a communications (e.g., code division multiple access) system. Power-efficient sign extension for Booth multiplication processes involves applying a sign bit in a Booth multiplication tree. The sign bit allows the Booth multiplication process to perform a sign extension step. This further involves one-extending a predetermined partial product row of the Booth multiplication tree using a sign bit for preserving the correct sign of the predetermined partial product row. The process and system resolve the signal value of the sign bit by generating a sign-extension bit in the Booth multiplication tree. The sign-extension bit is positioned in a carry-out column to extend the product of the Booth multiplication process. Then, the method and system form a final product from the Booth multiplication tree by adding the carry-out value to the sign bit positioned at least a predetermined column of the Booth multiplication tree. The result is to effectively extend the sum component of the final product with the sign and zero-extending the carry component of the final product.

Power-efficient sign extension for booth multiplication methods and systems

Techniques for the design and use of a digital signal processor, including (but not limited to) processing transmissions in a communications (e.g., CDMA) system. The disclosed method and system process interrupts arising in a multithreaded processor by receiving in an interrupt register a plurality of interrupts of a statistically indeterminate interrupt type and then associating a plurality of processing threads with the interrupt register for receiving the interrupt from the interrupt register. The method and system mask at least a subset of the plurality of processing threads so as to receive within each of the threads within the subset only ones of the plurality of interrupts of one or more predetermined types, thereby controlling on a per thread basis the processing of the plurality of interrupts according to the mask associated with a particular thread.

Shared interrupt control method and system for a digital signal processor

Growing community of inventors

Austin, TX, United States of America

William C Anderson