Other

Agere Systems Inc.

Lucent Technologies Inc.

Cisco Technology, Inc.

William Burdett Wilson

Kenneth Wade Paist

Mohammad Shafiul Mobin

James Arthur Bailey

Angelo Rocco Mastrocola

Mark Trafford

Un-Ku Moon

Lane Allen Smith

Jeffrey Lee Sonntag

Vladimir Sindalovsky

Bernard Lee Morris

Gregory W Sheets

Roger A Fratti

John Christopher Kriz

Dipankar Bhattacharya

Craig B Ziemer

Paul H Tracy

Shahriar Moinian

Weiwei Mao

Lisa Suzanne Wilson

Shye Shapira

Gerard Zaneski

Douglas Edward Sherry

Christopher John Abel

Tom Gibbons

Lisa Piper Jackson

In an improved sawhorse or clamp horse, a telescoping beam is pierced by a plaurlity of apertures at an insertion angle other than orthogonal to the surface, and a plualrity of push clamps, each bent at the insertion angle, is provided. By inserting a push clamp into the telescoping beam at an insertion angle, a work piece may be held securely in temporary positions during toolwork. The clamp horse's legs terminate in T-shaped feet to provide the option of permanent installation on the floor of the workspace.

Clamp horse

A device to be added to a walker. The device is used to monitor, correct, and improve the user's posture. The device is removably affixed to the walker and includes a pair of grips which monitor the amount of weight applied to the grips. The device further tracks the weight applied to the grips over time and provides feedback of the weight to the user via the monitor.

Posture improving device to attach to a walker

A drain wand includes an elongated wand body having an outside diameter of approximately &#xbc; inches. The wand body includes a first end that houses a water inlet unit and a valve controller. A sprayer is disposed along the second end of the elongated wand and is connected to the inlet unit and controller via an internal channel. The sprayer includes an elongated longitudinal opening that functions to discharge water at a generally perpendicular angle to the wand and at approximately 125 psi.

Drain wand

In one embodiment, a delay-locked loop (DLL) for synchronizing a phase of a periodic digital output signal with a phase of a periodic digital input signal includes a deskew element responsive to the periodic digital input signal to the DLL and the periodic digital output signal from the DLL for suppressing jitter in the periodic digital output signal by synchronizing transitions in the periodic digital output signal with transitions in the periodic digital input signal and generating a final jitter-suppressed periodic digital output signal.

Jitter suppression in type I delay-locked loops

Methods and apparatus are provided for a clock phase generator for CDR data sampling that generates early and/or late sampling clocks, relative to ideal transition and sample points. An early sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the transition clock signals to generate one or more early clock signals. A late sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the data sampling clock signals to generate one or more late clock signals. The early clock signals can be employed, for example, in a threshold-based decision feedback equalizer. The late clock signals can be employed, for example, in a classical decision feedback equalizer.

Method and apparatus for generating early or late sampling clocks for CDR data recovery

An IC inductor structure is provided which includes a first inductor element formed on a semiconductor substrate and at least a second inductor element formed on the semiconductor substrate proximate the first inductor element. The first inductor element has a first effective magnetic field direction associated therewith, and the second inductor element has a second effective magnetic field direction associated therewith. The first and second inductor elements are oriented relative to one another so as to create a non-zero angle between the first and second effective magnetic field directions.

Integrated circuit inductors with reduced magnetic coupling

Methods and apparatus are provided for clock skew calibration in a clock and data recovery system. One aspect of the invention compensates for skew among a plurality of clocks in a clock and data recovery system. The clocks are applied to a plurality of latches to sample an incoming signal. A reference signal, such as a Nyquist signal, is applied to a data input of each of the latches. Statistics of 'early' and 'late' corrections applied to at least one of the clocks by a bang-bang phase detector in the clock and data recovery system are evaluated and a delay of a clock buffer associated with the at least one clock is adjusted to obtain approximately a 50% early-to-late ratio for the at least one clock. The clock and data recovery system ensures that the early-to-late ratio for the sum of the plurality of clocks is approximately 50%.

Method and apparatus for clock skew calibration in a clock and data recovery system using multiphase sampling

A clock generator is provided for a transmitter in a transceiver adapted to communicate data over a serial data link. The transceiver includes a clock data recovery circuit recovers a receive clock signal and outputs a reference clock signal. The clock generator includes a local clock, a frequency difference detector, and a fractional-N frequency synthesizer. The local clock outputs a local clock signal. The frequency difference detector outputs a fractional frequency difference signal based on a frequency difference between the local clock signal and the reference clock signal. The fractional-N frequency synthesizer outputs a transmit clock signal having a same frequency as the recovered receive clock signal.

High-speed serial data link with single precision clock source

A circuit for spread spectrum rate control uses a first interpolator to phase interpolate between a first signal and a second signal and generate a first output signal based on a first control signal. A second interpolator is utilized to phase interpolate between a third signal and a fourth signal and generate a second output signal based on a second control signal. A multiplexer is used to select, based on a select signal, the first output signal or the second output signal as a spread spectrum clock (SSCLK). A leap-frog interpolator control is used to generate, in synchronism with the SSCLK, the first control signal based on a first type of phase adjustment request, the second control signal based on a second type of phase adjustment request, and the select signal to switch the multiplexer between the first output signal and the second output signal after allowing for an interpolator settling time when changing the first control signal or the second control signal.

Method and apparatus for generation of asynchronous clock for spread spectrum transmission

Various embodiments of the present invention provide systems and circuits for clock signal generation. For example, various embodiments of the present invention provide semiconductor devices that include a power source and a phase lock loop circuit. The power source provides a supply voltage to the phase lock loop circuit. The phase lock loop circuit includes and on-chip control voltage source and a voltage controlled oscillator. The on-chip control voltage source is capable of producing a control voltage that varies between a minimum voltage and a maximum voltage. The voltage controlled oscillator receives the control voltage and provides a clock signal with a frequency corresponding to the control voltage. The maximum voltage is greater than the supply voltage. For example, in some embodiments of the present invention, the maximum voltage is more than double the supply voltage. As another example, in some embodiments of the present invention, the maximum voltage is more than six times the supply voltage.

Internal supply voltage controlled PLL and methods for using such

Various embodiments of the present invention provide systems and circuits for processing information through comparison of input signals. For example, various embodiments of the present invention provide differential latch circuits. Such differential latch circuits include an input stage and a latch stage. The input stage provides an interim output that is available during a defined period, and the latch stage is operable to latch the temporary interim output during the defined period using a common clock.

Latch-based sense amplifier

Various apparatus and methods for related to clock recovery are disclosed. For example, in one illustrative embodiment, a clock recovery circuit includes a coding circuit adapted to translate a stream of first digital numbers derived from a source signal into a stream of first binary numbers and a stream of second binary numbers, a digital-to-analog converter (DAC) circuit coupled to the coding circuit and configured to provide an analog output based on the streams of first and second binary numbers and a voltage-controlled oscillator (VCO) controlled by the analog output of the DAC circuit and adapted to produce a base clock having a base clock frequency.

Methods and systems for coding of a bang-bang detector

In order to reduce the area of a charge pump PLL, one may separate proportional component and integral component of the loop filter voltage, and add additional circuitry so as to make the integral component appear as though it is affected by a much larger value of capacitance than is actually used. In an aspect, a current mirror may be used to subtract a portion of the integral component of the loop filter voltage from the total loop filter voltage. The difference signal is then used to drive an oscillator in the charge pump PLL. In another aspect, a third integrator or auto-calibration loop is used to set a center frequency of the oscillator.

Phase locked loop with scaled damping capacitor

A comparator circuit includes a reference generator connecting to a first source providing a first voltage. The reference generator is operative to generate a reference signal and includes a control circuit selectively operable in at least a first mode or a second mode in response to a first control signal, wherein in the first mode the reference signal is not generated, and in the second mode the reference generator is operative to generate the reference signal. The comparator circuit further includes a comparator connecting to a second source providing a second voltage, the second voltage being less than the first voltage. The comparator is operative to receive the reference signal and an input signal, and to generate an output signal which is a function of a comparison between the input signal and the reference signal. A hysteresis circuit is included in the comparator circuit for selectively controlling a switching threshold of the comparator, relative to the input signal, as a function of the output signal of the comparator. The comparator circuit includes a voltage clamp operative to limit a voltage applied to one or more devices in the control circuit, the comparator, and/or the hysteresis circuit to less than the second voltage.

Reliability comparator with hysteresis

Circuitry compensates for adverse effects resulting from leakage currents in loop filter capacitors for signal synthesizers, like PLLs. In one technique, leakage current in the loop filter's damping capacitor is compensated by driving the voltage across a matching capacitor and generating current for the damping capacitor based on current applied to the matching capacitor. In another technique, leakage current in the loop filter's transconductor capacitor is compensated by digitally accumulating differences between the damping capacitor voltage and a reference voltage, and then converting the accumulated difference into a (voltage or current) signal applied to the transconductor capacitor. In addition, the loop filter could have an analog transconductor path that generates a signal that is also applied to the transconductance capacitor. By effectively compensating for capacitor leakage currents, signal synthesizers of the present invention can be implemented using capacitors having thinner oxide gates, thereby reducing the size of the capacitors.

Growing community of inventors

Macungie, PA, United States of America

William Burdett Wilson