Micron Technology Incorporated

William Budge

Weimin Li

Gurtej S Sandhu

Christopher W Hill

Neal R Rueger

Zhiping Yin

John A Smythe

Jingyi Bai

A method including, prior to a plasma heat-up operation, forming a liner on structure coated with an insulator. And a method including forming a trench on a substrate, forming an insulator on the trench, and after forming a liner having a thickness of between about 50 angstroms and about 400 angstroms on the insulator, applying a plasma heat-up operation to the substrate.

Protection in integrated circuits

A low k interlevel dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. An oxide comprising interlevel dielectric layer comprising carbon and having a dielectric constant no greater than 3.5 is formed over the substrate. After forming the carbon comprising dielectric layer, it is exposed to a plasma comprising oxygen effective to reduce the dielectric constant to below what it was prior to said exposing. A low k interlevel dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. In a chamber, an interlevel dielectric layer comprising carbon and having a dielectric constant no greater than 3.5 is plasma enhanced chemical vapor deposited over the substrate at subatmospheric pressure. After forming the carbon comprising dielectric layer, it is exposed to a plasma comprising oxygen at a subatmospheric pressure effective to reduce the dielectric constant by at least 10% below what it was prior to said exposing. The exposing occurs without removing the substrate from the chamber between the depositing and the exposing, and pressure within the chamber is maintained at subatmospheric between the depositing and the exposing.

Low k interlevel dielectric layer fabrication methods

A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the trench. A silicon layer may be deposited on the base of the trench during the plasma process, or the plasma can treat the liner layer. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator, and oxidizing the silicon rich layer on the base of the trench. The resulting trench has a consistent etch rate from top to bottom of the trench.

Trench insulation structures including an oxide liner and oxidation barrier

A method including, prior to a plasma heat-up operation, forming a liner on a structure coated with an insulator. And a method including forming a trench on a substrate, forming an insulator on the trench, and after forming a liner having a thickness of between about 50 angstroms and about 400 angstroms on the insulator, applying a plasma heat-up operation to the substrate.

Method of forming an isolation structure that includes forming a silicon layer at a base of the recess

The invention includes a method of filling gaps in a semiconductor substrate. A substrate and a gas mixture containing at least one heavy-hydrogen compound are provided within a reaction chamber. The gas mixture is reacted to form a layer of material over the substrate by simultaneous deposition and etch of the layer. The layer of material fills the gap such that the material within the gap is essentially void-free. The invention includes a method of providing improved deposition rate uniformity. A material is deposited over a surface in the presence of at least one gas selected from the group consisting of D, HD, DT, Tand TH. The net deposition rate during the deposition has a degree of variance across the surface which is measurably improved relative to a corresponding degree of variance that occurs during deposition utilizing Hunder otherwise substantially identical conditions.

Methods of filling gaps using high density plasma chemical vapor deposition

Trench insulation structures including an oxide liner that is thinner along the walls of the trench than along the base

Methods of filling high aspect ratio trenches in semiconductor layers are provided. The methods utilize HDP-CVD processes to fill trenches with trench filling material. In the methods, the gas flow and RF bias are selected to provide a high etch to deposition ratio, while the trenches are partially filled. The gas flow and RF bias are then selected to provide a low etch to deposition ratio while the trenches are completely filled. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that is will not be used to interpret or limit the scope or meaning of the claims.

Methods for filling high aspect ratio trenches in semiconductor layers

A process for selectively depositing a silicon oxide layer onto silicon substrates of different conductivity types is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressures. Use of the process to produce layers, spacers, memory units, and gates is also disclosed, as well as the structures so produced.

Selectively deposited silicon oxide layers on a silicon substrate

Method of filling gaps and methods of depositing materials using high density plasma chemical vapor deposition

A process for enhanced selective deposition of a silicon oxide onto a substrate by pulsing delivery of the reactants through a linear injector is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressures. The ozone delivery is pulsed on and off. Optionally, the delivery of the ozone and the delivery of the TEOS are pulsed on and off alternately.

Use of linear injectors to deposit uniform selective ozone TEOS oxide film by pulsing reactants on and off

Low K interlevel dielectric layer fabrication methods

A low k inter-level dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. An oxide-comprising inter-level dielectric layer including carbon and having a dielectric constant no greater than 3.5 is formed over the substrate. After forming the dielectric layer, it is exposed to a plasma including oxygen effective to reduce the dielectric constant to below what it was prior to the exposing. A low k inter-level dielectric layer fabrication method includes providing a substrate having integrated circuitry at least patially formed thereon. In a chamber, an inter-level dielectric layer including carbon and having a dielectric constant no greater than 3.5 is plasma-enhanced chemical vapor deposited over the substrate at subatmospheric pressure. After forming the dielectric layer, it is exposed to a plasma including oxygen at subatmospheric pressure effective to reduce the dielectric constant by at least 10% below what it was prior to the exposing. The exposing occurs without removing the substrate from the chamber between the depositing and the exposing, and pressure within the chamber is maintained at subatmospheric pressure between the depositing and the exposing.

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Homedale, ID, United States of America

William Budge