Hewlett-packard Development Company, L.p.

William Bryson McHardy

Scott Lynn Michaelis

Anurupa Rajkumari

Mark D Frank

Kevin L Miller

Raymond Gratias

Peter Shaw Moldauer

Brian Nugent

According to one embodiment, a method comprises detecting loss of lockstep (LOL) for a processor in a multi-processor system. The method further comprises determining that the processor for which the LOL is detected is assigned the role of boot processor, and switching the role of boot processor to a spare processor without shutting down the system's operating system. In another embodiment, a method comprises system firmware determining that an LOL is detected for a lockstep pair of processors that are assigned the role of boot processor in a system. The method further comprises determining one of the lockstep pair of processors that is not the cause of the LOL, and copying the state of the determined one of the lockstep pair of processors that is not the cause of the LOL to a spare processor. The method further comprises switching the role of boot processor to the spare processor.

System and method for switching the role of boot processor to a spare processor responsive to detection of loss of lockstep in a boot processor

According to one embodiment, a method comprises detecting a loss of lockstep (LOL) for a processor module. The method further comprises determining a type of LOL that is detected, and, based at least in part on the determined type of LOL, determining a responsive action to take for the LOL. According to one embodiment, a method comprises detecting a loss of lockstep (LOL) for a processor module. The method further comprises using information identifying at least one of type of the detected LOL and source of the detected LOL to determine a responsive action to take for the LOL.

System and method for using information relating to a detected loss of lockstep for determining a responsive action

According to at least one embodiment, a method comprises detecting loss of lockstep for a pair of processors. The method further comprises triggering, by firmware, an operating system to idle the processors, and recovering, by the firmware, lockstep between the pair of processors. After lockstep is recovered between the pair of processors, the method further comprises triggering, by the firmware, the operating system to recognize the processors as being available for receiving instructions.

System and method for providing firmware recoverable lockstep protection

According to one embodiment, a method comprises assigning a first processor of a multi-processor system a role of spare processor for at least a second processor, and responsive to detecting loss of lockstep (LOL) for any of the at least a second processor, the first processor replaces the processor for which the LOL is detected. The method further comprises reestablishing lockstep for the processor for which the LOL is detected, and assigning the processor having its lockstep reestablished the role of spare processor for at least the first processor.

System and method for maintaining in a multi-processor system a spare processor that is in lockstep for use in recovering from loss of lockstep for another processor

A system comprises a processor module that supports lockstep mode of operation. The system further comprises non-volatile data storage having stored thereto configuration information specifying whether the processor module is desired to operate in lockstep mode. A method comprises storing configuration information to non-volatile data storage of a system, wherein the configuration information specifies whether lockstep mode of operation is desired to be enabled or disabled for a processor module of the system. The method further comprises causing, by the system, the processor module to have its lockstep mode enabled or disabled as specified by the configuration information.

System and method for configuring lockstep mode of a processor module

Systems, methods, software products test a memory cache of a processor that includes a test engine (e.g., a BISTE). High level test source code is formulated to use routines in API source code that, when compiled into machine test code, interfaces with the test engine. The machine test code is executed with the processor to test the memory cache to detect one or more faulty memory blocks in the memory cache. If any of the faulty memory blocks are detected, the test engine is instructed, through the machine test code, to set one or more bits in registers to functionally replace the faulty memory blocks with redundant blocks of the memory cache.

Test for processor memory cache

Techniques are disclosed for automatically synthesizing information from a plurality of computer-readable integrated circuit package models. In one embodiment, each of the plurality of package models contains information descriptive of a distinct package. Such information may include, for example, intra-package path lengths and/or propagation delays of signal nets in the modeled packages. Techniques are disclosed for automatically synthesizing such information to produce, for example, aggregate path lengths and/or propagation delays of the signal nets across all of the modeled packages. Such synthesis may be performed even when the package models use mutually inconsistent signal net naming conventions and the modeled packages are composed of different materials. Techniques are also disclosed for providing information to the package designer to assist the package designer in improving the design of the package models.

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Fort Collins, CO, United States of America

William Bryson McHardy