Intersil Americas Inc.

Other

Intersil Corporation

William Brandes Shearon

Salomon Vulih

Raymond L Giordano

Donald R Preslar

Sumer Can

William R Young

Robert H Isham

Paul K Sferrazza

Christopher Keith Davis

Paul J Graves

Peter G Klein

Lawrence Gilbert Gough

An integrated circuit comprises at least one pin and has at least one resistor connected between a reference voltage and the at least one pin. Current measurement circuitry applies a voltage across the at least one resistor and measures a current at the at least one pin responsive to the applied voltage in a first mode of operation. The measured current enables determination of a current limit set point for the integrated circuit. In a second mode of operation, the at least one resistor comprises a pull up resistor and the at least one pin that is connected to the at least one resistor comprises an open-drain output.

System and method for using an integrated circuit pin as both a current limiting input and an open-drain output

A tracking soft start circuit architecture contains a plurality of soft start circuits for generating a plurality of soft start voltages during startup for application to associated power supply terminals of a power supply system. The soft start circuits are interconnected in such a manner that prevents any soft start circuit from generating a soft start voltage waveform until all of the controlled power output devices have been brought to the same prescribed state of operation, that is, all power FET gates are precharged and their source voltages match each other.

Tracking soft start circuit for generating a plurality of soft start voltages where all soft start voltages are prevented until all have been brought to the same prescribed state of operation

A cascaded DC-DC converter architecture has an upstream converter stage and a downstream converter stage, which derives its input voltage from the upstream stage. Cascading the two converter stages enables functionality of control and monitoring (including soft start and overcurrent detection) circuitry of the upstream stage to be used for the downstream stage, to reduce chip area, cost, and complexity. A voltage window regulator in the downstream converter ensures that, during shutdown, its output voltage will be maintained within a prescribed window of its regulated output voltage, so that no soft start delay is needed when the second converter stage is turned back on.

Integrated circuit for generating a plurality of direct current (DC) output voltages

The current limiting circuit of the present invention includes a transconductance amplifier having two outputs and forming a conventional feedback loop. A first output connects to an output transistor and a second output is a replica output used to form a rapid response feedforward path to control the gate of the output transistor, for example, an external MOSFET.

Current limiting circuit with rapid response feedback loop

At least upper order stages of a multi-stage charge pump contain respective drive signal recovery circuits, that enable the charge pump to operate over a larger voltage range and/or be driven by a very small input voltage. The switch control signal recovery circuit has an auxiliary NFET switch whose current flow path is series-coupled with a Schottky diode between the output voltage of the next lower order stage and a PFET switch drive line. The auxiliary switch controllably clamps the PFET switch drive line at a voltage that differs from the output voltage of the next lower order charge pump stage by the voltage drop across the Schottky diode. This effectively guarantees that the level-shifted line of that stage's transient clamp network will be biased to its appropriate operating voltage level, so that the clamp rail of this stage cannot hang up at a voltage level that is well below the output voltage from the next lower order stage.

Charge pump drive signal recovery circuit

The integrated circuit includes a power driving device, and a pilot device for sensing current through the power driving device. The pilot device includes a composite pilot having a plurality of series connected transistors and which is at least active while the power driving device is in a linear mode, and a secondary pilot which is active while the power driving device is in a saturation mode. Also, a control circuit activates the secondary pilot.

Integrated circuit with current sense circuit and associated methods

The integrated circuit includes a power FET for generating an output voltage, a pilot FET for sensing current through the power driving device and generating a reference voltage, and an amplifier circuit for comparing the reference voltage of the pilot device with the output voltage of the power driving device. The amplifier circuit includes a differential pair of matched bipolar junction transistors (BJTs) having a common base. A first BJT of the differential pair being diode-connected. The amplifier circuit controls the gates of the power FET and the pilot FET.

Integrated circuit with current-limited power output and associated method

An oscillator includes a first sawtooth waveform generator for generating a first sawtooth waveform having a selectively started ramp portion and a second sawtooth waveform generator for generating a second sawtooth waveform having a selectively started ramp portion. A controller is also included for alternatingly controlling the first and second sawtooth waveform generators so that a transition to the ramp portion of one sawtooth waveform is based upon determining the ramp portion of the other sawtooth waveform reaching a trip point. The controller also sets the trip point substantially independent of a supply voltage so that the oscillator has reduced sensitivity to supply voltage changes.

Oscillator having reduced sensitivity to supply voltage changes

In a bus driver circuit having a floating gate circuit for controlling voltage on the gate of the output driver and a floating well circuit for controlling voltage on the body of the output driver, the improvement comprising a well pull up circuit coupled to the output driver for applying supply voltage to the body during transmission and for applying the output of the floating gate circuit to the body during quiescence.

Backwards drivable MOS output driver

A bus driver circuit has floating gate circuits with three transistors. Two of the transistors for an inverter for operating the output power transistor. The third transistor is connected to receive control signals from well pull circuits. The control signal keeps the third transistor off when the bus driver circuit is not enabled.

Floating gate circuit for backwards driven MOS output driver

A charge pump circuit includes a plurality of pumping capacitors, a plurality of switches connected to the pumping capacitors, and a controller for generating first and second sets of switch control signals for controlling the switches so that the pumping capacitors generate either an increased or a negative output voltage. The controller includes a clock having first outputs for the first set of switch control signals, a transient clamp network having second outputs for the second set of switch control signals, and a respective level shifting capacitor connected between each first output and a corresponding second output and cooperating with the transient clamp network so that the second set of signals is level shifted from the first set.

Cascadable, high efficiency charge pump circuit and related methods

A constant slew rate amplifier has a precision internal slew rate control reference, that generates respective positive-going and negative-going voltages, associated with corresponding excursions in the input signal. These slew rate-defining voltages are decoupled from the line, making it possible to drive the line with an amplified output signal that faithfully follows the input signal and conforms with prescribed slew rate and rise/fall time specifications, irrespective of the capacitance of the line. In addition, the constant slew rate amplifier of the present invention is configured to minimize power dissipation during non-transitional signal conditions, while providing substantial current to rapidly drive the line from one state to another in accordance with the input signal.

Growing community of inventors

Findlay, OH, United States of America

William Brandes Shearon