Altera Corporation

William Bradley Vest

Myron Wai Wong

Irfan Rahim

Andy Louie Lee

Thomas Henry White

Jeffrey T Watt

Dirk Alan Reese

John C Costello

Ping-Chen Liu

Thien Le

Leo Min Maung

Qi Xiang

Paul Leventis

Jun Liu

Albert Ratnakumar

Jeffrey Xiaoqi Tung

Lu Zhou

Gwen G Liang

Sriram Muthukumar

Yanzhong Yu

Power supply decoupling capacitors are provided for integrated circuits. The decoupling capacitors may be distributed in clusters amongst powered circuit components. Each cluster may contain a number of individual capacitor cells that are connected in parallel. Each capacitor cell may contain a capacitor and a resistor connected in series with the capacitor. The capacitors may be metal-insulator-metal (MIM) capacitors. The resistor in each cell may limit the current through an individual capacitor in the event of a short in the capacitor due to a dielectric defect.

Integrated circuit decoupling capacitors

Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. Each memory element may each have four inverter-like transistor pairs that form a bistable element, a pair of address transistors, and a pair of relatively weak transistors connected between two of the inverters that create a common output node which is resistant to rapid changes to its state. The transistors may be connected in a pattern that forms a bistable memory element that is resistant to soft error upset events due to radiation strikes. Data may be loaded into and read out of the memory element using the address transistor pair.

Memory elements with soft error upset immunity

Memory elements are provided that exhibit immunity to soft error upsets. The memory elements may have cross-coupled inverters. The inverters may be implemented using programmable Schmitt triggers. The memory elements may be locked and unlocked by providing appropriate power supply voltages to the Schmitt trigger. The memory elements may each have four inverter-like transistor pairs that form a bistable element, at least one address transistor, and at least one write enable transistor. The write enable transistor may bridge two of the four nodes. The memory elements may be locked and unlocked by turning the write enable transistor on and off. When a memory element is unlocked, the memory element is less resistant to changes in state, thereby facilitating write operations. When the memory element is locked, the memory element may exhibit enhanced immunity to soft error upsets.

Volatile memory elements with soft error upset immunity

Power regulator circuitry for programmable memory elements on programmable logic device integrated circuits is provided. The programmable memory elements may each include a storage element formed from cross-coupled inverters and an address transistor. Address drivers may be used to supply address signals to the address transistors. The power regulator circuitry may include an address power supply circuit that produces a time-varying address power supply voltage to the address drivers and storage element power supply circuits that provide time-varying storage element power supply voltages to the cross-coupled inverters in the storage elements. Unity gain buffers may be used to distribute a reference voltage from a bandgap voltage reference to the power supply circuits. The power supply circuits may use voltage dividers and p-channel metal-oxide-semiconductor control transistors.

Power regulator circuitry for programmable logic device memory elements

An integrated circuit with memory elements is provided. The memory elements may have memory element transistors with body terminals. Body bias control circuitry may supply body bias voltages that strengthen or weaken memory element transistors to improve read and write margins. The body bias control circuitry may dynamically control body bias voltages so that time-varying body bias voltages are supplied to memory element transistors. Address transistors and latch transistors in the memory elements may be selectively strengthened and weakened. Process variations may be compensated by weakening fast transistors and strengthening slow transistors with body bias adjustments.

Memory elements with body bias control

Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair of cross-coupled inverters are connected to the capacitor. The inverters ensure that the memory elements produce output control signals with voltages than range from one power supply rail to another. Each configuration random-access memory element may have a clear transistor. The capacitor may be formed in a dielectric layer that lies above the transistors of the inverters, the address transistor, and the clear transistor. The inverters may be powered with an elevated power supply voltage.

Configuration random access memory

A power-on-reset circuit determines when it is safe for a programmable device to access configuration data from an associated non-volatile memory following a reset operation. The power-on-reset circuit receives a bandgap reference voltage produced by the programmable device. A comparator circuit is used to trigger a self-clocking delay unit when the bandgap reference voltage reaches a threshold level. The self-clocking delay unit generates its own clock signal independent of the clock frequency of the programmable device. The self-clocking delay unit may use edge-dependent delay units in a feedback loop to generate the clock signal. Using its own clock signal, the self-clocking delay unit waits for a predetermined time period and the outputs a signal to be used to enable access to the associated non-volatile memory.

Process and temperature invariant power on reset circuit using a bandgap reference and a long delay chain

A programmable logic device integrated circuit or other integrated circuit may have logic circuitry that produces data signals. The data signals may be routed to other logic circuits through interconnects. The interconnects may be programmable. A level recovery circuit may be used at the end of each interconnect line to strengthen the transmitted data signal. The level recovery circuit that is attached to a given interconnect line may produce true and complementary versions of the data signal that is on that interconnect line. Level shifting circuitry may be provided to boost the data signals on the interconnects. Each interconnect line may have a level shifter circuit that receives the true and complementary versions of a data signal and that produces corresponding boosted true and complementary versions of the data signal. The boosted signals may be provided to the control inputs of complementary-metal-oxide-semiconductor transistor pass gates in programmable look-up table circuitry.

Look-up table overdrive circuits

Circuits and methods for reducing power consumption in an Integrated Circuit (IC) are provided. In one embodiment, a circuit includes a POR system control circuit, a POR latch and a control block circuit. The POR system control circuit generates a pulse during power up which is sent to the POR latch to set the state of the POR latch to a first logic state. The state of the POR latch is used to enable POR circuits during power up. The control block generates an output to disable POR circuits in the IC based on the state of the POR latch. After power-up, the state of the POR latch is set to a second logic state in order to disable the POR circuits resulting in power savings in the IC by eliminating static POR circuit current.

Reducing power consumption by disabling power-on reset circuits after power up

Techniques and circuitry provide fast, accurate, proper, and reliable transfer of configuration data from an on-chip nonvolatile memory to the programmable logic core of a programmable logic integrated circuit. A first technique includes not allowing the programmable logic to be configured until the data held in the on-chip nonvolatile memory can be read correctly and reliably. A second technique includes verifying the configuration data is transferred from the nonvolatile memory to the programmable logic core correctly and without error during the transfer process. These two techniques may be combined or used individually during the configuration of an integrated circuit.

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San Jose, CA, United States of America

William Bradley Vest