Nvidia Corporation

William B Simms

Russell R Newcomb

Barry A Wagner

Michael B Diamond

William Tsu

Oren Rubinstein

Ashfaq Shaikh

Luc R Bisson

Ting-Sheng Ku

Ting Ku

Wei Huang

An interface for implementing a loopback configuration which offers improved calibration and/or testing of an electronic system is disclosed. More specifically, embodiments provide a bi-directional interface with at least two portions or partitions capable of communicating data in opposite directions and implementing a loopback configuration between components of an electronic system, thereby enabling more flexible, efficient and effective calibration and/or testing of the electronic system using a single interface. The loopback of the partitioned bi-directional interface may be used to perform data link training and/or electronic system testing. In one embodiment, the loopback configuration of the interface may be reversible. Additionally, the looped or coupled end of the partitions may be switched from one component to another, thereby reversing the configuration of the loopback in one embodiment. As such, embodiments enable different and/or additional calibration operations and/or tests to be performed when compared with conventional loopback configurations.

Loopback configuration for bi-directional interfaces

A method of receiving data. A plurality of data signals and clocking signals are received over a source synchronous communication channel. The plurality of data signals is strobed with the clocking signal at a plurality of coarse time offset delays (e.g., time offset delays spanning over a data bit period). The plurality of error rates associated with the strobing at the plurality of coarse time offset delays is determined. Strobing design of a transmitting component (e.g., edge-strobed, center-strobed, etc.) may be determined based on the plurality of error rates. The error rates of the plurality of data signals strobed with a plurality of time offset delays close to the determined strobing design of the transmitting component is calculated. A time offset delay is selected based on the error rates. The plurality of data signals can be strobed with the selected time offset delay to recover the transmitted data signals.

Method and system for a free running strobe tolerant interface

System and apparatus for capacitively coupling signals with an integrated circuit (IC) are described. Capacitive elements disposed with a transmitting IC effectively function as AC coupling capacitors for a PCIe, DisplayPort&#x2122; or other interconnect linking the transmitting IC with a receiver disposed remote there from. Integrating the coupling capacitors allows for a smaller and more economical design for the circuits that utilize the interconnect.

Techniques for capacitively coupling signals with an integrated circuit

Systems and apparatus for capacitively coupling signals with an integrated circuit (IC) are described. Capacitive elements disposed within a transmitting IC effectively function as AC coupling capacitors for a PCIe, DisplayPort&#x2122; or other interconnect linking the transmitting IC with a receiver disposed remote there from. Integrating the coupling capacitors allows for a smaller and more economical design for the circuits that utilize the interconnect.

System and apparatus for capacitively coupling signals with an integrated circuit

Embodiments for binary encoding and/or decoding data are disclosed. In one or more embodiments, N data bits may be encoded using one of a plurality of codes derived from at least N+1 bits wherein said one of the plurality of codes is selected to most closely maintain a programmable non-equal ratio of bits at a first logical level to bits at a second logical level.

Binary data encoding/decoding such as for communicating between computing platform components over a parallel interconnect

Embodiments for binary encoding and/or decoding of data for transmission and/or reception over a data interconnect are disclosed. For an embodiment, a code may comprise a base portion, a subset of the base portion, a complement bit associated with the base portion, and a complement bit associated with the subset of the base portion.

Binary data encoding/decoding for parallel bus

Embodiments for binary encoding and/or decoding data are disclosed. In or more embodiments, N data bits may be encoded using one of a plurality of codes derived from at least N+1 bits wherein each of the plurality of codes comprises approximately equal numbers of bits at a first logical level and a second logical level.

Binary data encoding/decoding with error detection, such as for communicating between computing platform components

A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, clock buffers not required to drive active data lanes are placed in an inactive state to reduce clock power dissipation.

Logical-to-physical lane assignment to reduce clock power dissipation in a bus having a variable link width

An arrangement provides for further power reduction where a system includes two or more electrical components that can be placed into two or more power consumption states. The arrangement can take advantage of existing circuitry to selectively disable certain state transition detectors to thereby provide additional power reduction.

Method and apparatus for controlling power state of a multi-lane serial bus link having a plurality of state transition detectors wherein powering down all the state transition detectors except one

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San Jose, CA, United States of America

William B Simms