Hewlett-packard Company

Hewlett-packard Development Company, L.P.

Google Inc.

Institute for the Development of Emerging Architectures, L.l.c.

William B Buzbee

James S Mattson

Lacky V Shah

David A Dunn

Manuel Enrique Benitez

Daniel Reuben Bornstein

Lacky Shah

Michelle A Ruscetta

Ben C Cheng

Carol Linda Thompson

Steven O Miller

Carl D Burch

David E De Bellis

Anthony Fitzgerald Istvan

Cary Coutant

Daniel L Stuart

The present disclosure relates to techniques for potentially increasing the reliability and/or stability of systems having virtual machines that support multiple modes of execution. For example, as described herein, a virtual machine partitions a plurality of program instructions into a plurality of traces for execution by a virtual machine operating on a computing device, wherein the virtual machine has first and second modes of execution, and wherein each of the plurality of traces comprises one or more of the plurality of program instructions. The virtual machine applies the second mode of execution to a first trace in the plurality of traces and determines an error condition that is caused by the application of the second mode of execution to the first trace. After determining the error condition, the virtual machine applies the first mode of execution to the first trace to recover the virtual machine from the error condition.

Fault-resistant just-in-time compiler

A method of printing a document having a plurality of pages in an original sequence includes determining an second sequence to print each of the pages, wherein the second equence is different than the original sequence; loading each of the pages onto cyclic multi-page transport apparatus according to the optimal sequence; and unloading the pages from the transport apparatus according to the original sequence.

Method of printing a multi-page document using a cyclical multi-page transport apparatus

A blocking system intercepts communications between a software program and an operating system in order to handle blocking and unblocking of event signals. The blocking system intercepts system calls to the operating system requesting the blocking and unblocking of event signals and keeps track of which event signals are blocked and unblocked without delivering the system calls to the operating system. The blocking system also intercepts event signals from the operating system and only allows unblocked event signals to pass to the software program. Blocked event signals received by the blocking system are discarded until the program unblocks the blocked event signals. After unblocking an event signal, the blocking system determines whether a corresponding event signal was previously received and blocked. If so, the blocking system transmits a signal indicating that the event corresponding to the event signal occurred.

System and method for efficiently blocking event signals associated with an operating system

Dynamic translation is used during debugging of a computer application process. The computer application process resides in a computing system in which blocks of code within a shared library are utilized by the computer application process. The blocks of code within the shared library are also available to be utilized by other applications in the system. During runtime, the computer application process is dynamically translated to produce translated code. The dynamic translation includes translation of a first block of code within the shared library to produce a translated block of code. The translated block of code is included within the translated code. Debugging code, such as a break instruction, may then be added to the translated code. Alternatively, only blocks of code within the shared library which are called by the computer application process or modified by a debugger are dynamically translated. In this alternative case, the object code for the computer application process is executed without being dynamically translated.

Use of dynamic translation to provide breakpoints in non-writeable object code

A computer-implemented system, method, and product are provided for multi-branch backpatching in a dynamic translator. Such backpatching typically increases the speed of execution of translated instructions by providing a direct control path from translated multi-branch-jump instructions to their translated target instructions. In one embodiment, the multi-branch backpatching dynamic translator undertakes backpatching on an &ldquo;as-needed&rdquo; basis at run time. That is, backpatching is done for those branch targets that are executed rather than for all branch targets, or rather than for those branch targets that are estimated or assumed will be executed. Such backpatching is accomplished in one embodiment by generating dynamic backpatching code specific to each translated multi-branch-jump instruction. A multi-branch jump, or switch, table of each multi-branch-jump instruction is initialized so that all entries direct control to the dynamic backpatching code for that instruction. As branches of the multi-branch-jump instruction are executed, the dynamic backpatching code enables a backpatcher that replaces the corresponding entry in the translated multi-branch-jump table with pointers to the address of the translated target address, if present.

System, method, and product for multi-branch backpatching in a dynamic translator

A translating software emulator designed for converting code from a legacy system to a target system and fully preserving the synchronous exception state while still allowing for full and aggressive optimization in the translation. A user application is translated to a target system using full optimization techniques. The translation may be done dynamically by an emulator emulating the legacy system on the target system, or the translation may be a static translation or a compilation, fully generating a new executable program operable on the target system. The invention recovers from the exception properly by restoring the target machine state to the machine state expected by the legacy system. This recovery is done by using an exception delivery mechanism to restore the machine state of the target system before executing the exception handling code. The restoration of the machine state is done by executing a recovery block generated by the translation that modifies the machine state to match the legacy machine state.

Method and apparatus for a translation system that aggressively optimizes and preserves full synchronous exception state

A method and system for relating profile data generated by monitoring the execution of an optimized machine-code computer program back to the source-language description of the computer program. Logical line numbers are associated with the basic blocks of the intermediate-code representation of the computer program and actual line numbers are associated with each instruction of the intermediate-code representation of the computer program. During optimization of the intermediate code, the logical line numbers remain fixed to basic blocks, while actual line numbers remain fixed to intermediate-code instructions. A branch instruction and the target of the branch instruction in the optimized machine-code computer program or in an optimized assembly-language computer program can be related back to source-language statements by using the actual line number associated with the branch instruction and the logical line number associated with the basic block that contains the target of the branch instruction.

Method and system for correlating profile data dynamically generated from an optimized executable program with source code statements

Method for a translation system that aggressively optimizes and preserves full synchronous exception state

The present invention is a system, method, and product for improving the speed of dynamic translation systems by efficiently positioning translated instructions in a computer memory unit. More specifically, the speed of execution of translated instructions, which is a factor of particular relevance to dynamic optimization systems, may be adversely affected by inefficient jumping between traces of translated instructions. The present invention efficiently positions the traces with respect to each other and with respect to &ldquo;trampoline&rdquo; instructions that redirect control flow from the traces. For example, trampoline instructions may redirect control flow to an instruction emulator if the target instruction has not been translated, or to the translation of a target instruction that has been translated. When a target instruction has been translated, a backpatcher of the invention may directly backpatch the jump to the target so that the trampoline instructions are no longer needed. A method of the present invention includes: (,) designating &ldquo;chunks&rdquo; of memory locations, and (,) positioning a translated trace and its corresponding trampoline instructions in the same chunk. The size of the chunk generally is based on a &ldquo;machine-specific shortest jump distance&rdquo; that is the shortest maximum distance that a jump instruction may specify. In particular, the chunk length may be determined so that, for every translated trace and trampoline instruction positioned in the same chunk, the greatest distance between a translated jump instruction and its target trampoline instruction is not greater than the machine-specific shortest jump distance for that type of jump instruction.

System, method, and product for memory management in a dynamic translator

A method and system of dynamically translating code that uses code annotations to determine whether the dynamic translator must fully materialize machine state. At compilation time, annotations are placed in an application's executable file indicating the number of formal parameters expected by each of the application's entry points. When the application is dynamically translated, the dynamic translation system (DTS) aggressively translates the application. Therefore, the DTS does not generate instructions for materializing the machine state at potential stopping points. When the application makes a system call that arms an exception handler, the DTS looks to the annotations to determine the number of formal parameters expected by the handler. If an exception handler expects two or fewer parameters, then that handler does not use the machine state. Conversely, if a handler expects three or more parameters, then that handler may use the machine state. Therefore, if the handler only has two formal parameters, then the DTS continues to aggressively translate the application program. Otherwise, the DTS discards all of the previously translated code and starts conservatively translating the application.

System and method of using annotations to optimize dynamically translated code in the presence of signals

A run-time optimization strategy uses a trace picker to identify traces of program code in a native code pool, and a translator to translate the traces into a code cache where the traces are executed natively. Static branch prediction hints are encoded in branch instruction in the translated traces. A program module implementing the present invention is initialized with an empty code cache and a pool of instruction in a native code pool. The trace picker analyzes the instructions in the native code pool and identifies traces of instructions that tend to be executed as a group. When a trace is identified, basic blocks lying along the trace path are translated into a code cache, with static branch predictions encoded into the branch instructions of the basic blocks based on branching behavior observed when the trace is identified. Control then passes to the basic blocks in the code cache, and the basic blocks in the code cache are executed natively using the static branch prediction hints encoded into the branch instructions.

Method and apparatus for using static branch predictions hints with dynamically translated code traces to improve performance

The inventive mechanism allows an application to switch modes during its operation, between a compatibility or legacy mode for a previous architecture, and a native mode for a current architecture. The mechanism includes an official function descriptor which describes information for accessing a function which resides in one module. The OFD has a legacy portion is useable by a legacy module and a native portion is useable by a native module. The mechanism also includes a linkage table that resides in a second module which references the function in the first module. The portion of the OFD which corresponds to the mode of the linkage table module is copied into the linkage table. Each portion contains one entry that corresponds to an address location of the function, and another entry that is a value for a register which refers to the data segment corresponding to the load module containing the function. The information in the OFD depends on whether the function is a legacy function or a native function.

Method and apparatus for the inter-operation of differing architectural and run time conventions

A computer-implemented system, method, and product are provided to designate and translate traces of original instructions of an executable file at run time based on dynamic evaluation of control flow through frequently executed traces of instructions. Such designation typically reduces unnecessary translations and optimizations, and thereby increases execution speed and reduces the usage of memory and other resources. The invention includes a hot trace identifier to identify frequently executed traces of instructions and a hot trace instrumenter to instrument such frequently executed traces so that control flow through them may be recorded. If the amount or rate of control flow through a frequently executed trace exceeds a threshold value, a hot trace selector is invoked to select a hot trace of original instructions including those of the frequently executed trace. The hot trace may be dynamically optimized. The system, method, and product also provide for the continuous recording of control flow through hot traces. If control flow has changed during execution, such that the amount or rate of control flow through a hot trace falls below a threshold value, the trace may be removed.

Control path evaluating trace designator with dynamically adjustable thresholds for activation of tracing for high (hot) activity and low (cold) activity of flow control

Growing community of inventors

Half Moon Bay, CA, United States of America

William B Buzbee