Silicon Laboratories Inc.

Applied Micro Circuits Corporation

William Anker

Srisai Rao Seethamraju

James David Barnette

Xue-Mei Gong

Timothy A Monk

Aslamali A Rafi

Ronald B Hulfachor

Gary D Martin

Rajesh Thirugnanam

Richard J Juhn

A method for operating a clock product includes selectively coupling a first output divider and a second output divider based on a determination of whether the first divider value is integrally related to the second divider value. In response to the first divider value being integrally related to the second divider value, the selectively coupling includes cascading the first output divider with the second output divider. In in response to the first divider value being non-integrally related to the second divider value, the selectively coupling includes configuring the second output divider to be cascaded with a first phase-locked loop and in parallel with the first output divider and to be responsive to an error correction signal based on a difference in response times of the first output divider and the second output divider to a change in a filtered phase difference signal of the first phase-locked loop.

Synchronization of clock signals generated using output dividers

A phase and frequency detector receives a reference clock signal with a period error and receives a feedback clock signal from a feedback divider. The feedback divider circuit divides a clock signal from a voltage controlled oscillator. The feedback divider divides by different divide values during odd and even cycles of the reference clock signal to cause the feedback clock signal to have a period error that substantially matches the period error of the reference clock signal. The divider values supplied to the feedback divider are determined, at least in part, by the period error of the reference clock signal.

Correction for period error in a reference clock signal

A method includes generating a filtered phase difference signal based on a reference clock signal and a feedback clock signal. The method includes generating a first output clock signal based on a first divider control signal and an input clock signal. The feedback clock signal is based on the first output clock signal. The method includes generating a first time code based on a counter signal and a first update of the first output clock signal in response to an update of the filtered phase difference signal to a first value from a second value. The second output clock signal is based on a second divider control signal, the input clock signal, and an error correction signal generated based on the first value, the second value, the first time code, and the second time code. The first and second divider control signals are based on the filtered phase difference signal.

Two sets of information (phase and cycle count) that are created asynchronously in a voltage controlled oscillator based analog-to-digital converter. A third set of information is created that is a delayed cycle count. The three sets of information are used to determine the proper alignment of the phase and the cycle count.

Aligning asynchronous signals by time shifting information

An integrated circuit receives a first and second clock signal and a select signal that selects one of the clock signals. A glitchless switching circuit supplies an output clock signal according to which of the first and second clocks is selected by the select signal. A reset circuit coupled to the glitchless switching circuit responds to a direction of a transition of the select signal and generates a first reset signal in response to a first direction of the transition and generates a second reset signal in response to a second direction of the transition. The reset pulses are supplied respectively to first and second paths in the glitchless switching circuit to reset the state machine formed by the first and second paths in the event one of the input clocks is absent.

Glitchless clock switching that handles stopped clocks

A crystal offset value is stored in non-volatile memory in an oscillator device. The crystal offset value corresponds to a ratio between a rated frequency of an output of a crystal oscillator and a measured frequency of the output of the crystal oscillator. A rated divide value that corresponds to a selected frequency for an output of the oscillator device assumes the crystal oscillator operates at its rated or ideal frequency. Thus, the rated divide value corresponds to the rated frequency. The rated divide value is adjusted by the crystal offset value to generate an adjusted divide value and the adjusted divide value is used to generate an output signal of the oscillator device with the selected frequency.

Compensation for crystal offset in PLL-based crystal oscillators

A technique that is readily implemented in monolithic integrated circuits includes a phase-locked loop (PLL) that generates an output clock signal based on a reference clock signal and selectable configuration parameters. A method includes providing to a PLL circuit, selected configuration information based, at least in part, on a selected frequency of a reference clock signal and a selected PLL bandwidth. The method includes generating an output clock signal, by the PLL circuit, based, at least in part, on the reference clock signal and the selected configuration information. The method includes storing in a storage circuit, a plurality of sets of configuration information corresponding to a range of frequencies of the reference clock signal and a range of PLL bandwidths. The selected configuration information is accessed from the plurality of sets of configuration information according to the selected frequency and the selected bandwidth.

Programmable phase-locked loop responsive to a selected bandwidth and a selected reference clock signal frequency to adjust circuit characteristics

A SONET multiplexed communications system that facilitates the sharing of processing resources while reducing overall system complexity. The SONET multiplexed communications system includes a single multi-output pointer generator clocked by a system clock and a plurality of clock domain transfer circuits having respective FIFO buffers for transferring SONET signals from the system clock domain to respective outgoing line clock domains. The multi-output pointer generator and the clock domain transfer circuits compensate for timing differences between the system clock and the respective outgoing line clocks by either skipping or overwriting FIFO buffer address locations corresponding to TOH byte positions in outgoing SONET frames. The TOH bytes corresponding to the skipped or overwritten TOH byte positions are subsequently re-generated by respective TOH insertion circuits before the outgoing SONET frames are passed through outgoing SONET lines.

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Londonderry, NH, United States of America

William Anker