Advanced Micro Devices Corporation

Globalfoundries Inc.

Samsung Electronics Co., Ltd.

Verifai Inc.

William Alexander Hughes

Vydhyanathan Kalyanasundharam

Derrick R Meyer

Dale E Gulick

Kiran Bondalapati

Philip Enrique Madrid

Greggory D Donley

Scott A White

Geoffrey S Strongin

Kevin John McGrath

Michael K Fertig

Larry David Hewitt

David S Christie

Benjamin Tsien

Kevin Michael Lepak

Patrick N Conway

Scott E Swanstrom

Frank P Helms

Stephen C Ennis

William Kurt Lewchuk

Chen-Ping Yang

Samuel D Naffziger

Benjamin T Sander

Michael T Clark

John P Petry

Gerald David Zuraski, Jr

Paul C Miranda

Chetana Nagendra Keltcher

Hebbalalu S Ramagopal

James B Keller

Mark Douglas Hummel

Frederick Daniel Weber

Alexander Klaiber

Jeffrey Roy Dwork

Mitchell K Alsup

Narsing Krishna Vijayrao

Eric M Rentschler

Roger Dwain Isaac

Andrew William Lueck

Teik-Chung Tan

Michael Haertel

Andrew McBride

Aaron Joseph Grenat

Sridhar P Subramanian

James S Roberts

Creigton S Asato

Jody A McCoy

Bruce R Holloway

Ajay Naini

Sandeep Srinivasan

Jeremy Schreiber

Hao Huang

Richard Brunner

Yinong A Zhang

Stephen M Conor

Rohit Uday Suvarna

Chengping Yang

Chenping Yang

Methods, systems, and devices for tuning a set of simulation parameters associated with a design verification environment are described that include: simulating a circuit design according to a set of simulation runs; providing, to a machine learning network, an indication of functional coverage results associated with simulating the circuit design according to the set of simulation runs; receiving an output in response to the machine learning network processing the functional coverage results; and simulating the circuit design based on a recommended set of simulation parameters. The output includes: an indication of a near miss event associated with the functional coverage results; and the recommended set of simulation parameters. Simulating the circuit design based on the recommended set of simulation parameters includes generating a set of component signals associated with triggering the near miss event.

Method and system for using deep learning to improve design verification by optimizing code coverage, functional coverage, and bug detection

According to one general aspect, a method of performing a cache transaction may include transmitting a cache request to a target device. The method may include receiving a cache response that is associated with the cache request. The method may further include completing the cache transaction without transmitting an exclusive cache response acknowledgement message to the target device.

Removal and optimization of coherence acknowledgement responses in an interconnect

A method and apparatus for selectively bypassing a cache in a processor of a computing device are disclosed. A mechanism to provide visibility to transactions on the core to a cache interface (e.g., an L3 cache interface) in a trace controller buffer (TCB) for debugging purposes, by causing selected transactions, which would otherwise be satisfied by the cache, to bypass the cache and be presented to the memory system where they may be logged in the TCB is described. In an embodiment of the invention, there is provided a method for providing processing core request visibility comprising bypassing a higher level cache in response to a processing core request, capturing the processing core request in a TCB, providing a mask to filter the processing core request, and returning a transaction response to a requesting processing core.

Method and apparatus for selectively bypassing a cache for trace collection in a processor

A device includes a link interface circuit, a first plurality of allocated buffers, and a second plurality of non-allocated buffers. The link interface circuit is operable to communicate over a communications link using a plurality of virtual channels. A different subset of the plurality of allocated buffers is allocated to each of the virtual channels. The non-allocated buffers are not allocated to a particular virtual channel. The link interface circuit is operable to receive a first transaction over the communications link and assign the first transaction to one of the allocated buffers or one of the non-allocated buffers.

Buffer management using freelist buffers

A crossbar switch with primary and secondary pickers is described herein. The crossbar switch includes a crossbar switch command scheduler that schedules commands that are to be routed across the crossbar from multiple source ports to multiple destination ports. The crossbar switch command scheduler uses primary and secondary pickers to schedule two commands per clock cycle. The crossbar switch may also include a dedicated response bus, a general purpose bus and a dedicated command bus. A system request interface may include dedicated command and data packet buffers to work with the primary and secondary pickers.

Crossbar switch with primary and secondary pickers

A processor power limiter and method is provided. The processor includes a first programmable location configured to store a processor power target. A power monitor is configured to estimate a power dissipation due to processor load. A power controller is configured to adjust a processor power parameter based on the power target and the power dissipation. The processor may include an interface for an operating system. A second programmable location may be configured to store a software processor power target accessible by the operating system. The processor may also include a sideband interface for an external agent. A third programmable location may be configured to store an agent processor power target accessible by the external agent. The power controller may be configured to adjust a processor core voltage and/or frequency such that the power dissipation stays below the processor power target, software processor power target and the agent processor power target.

System for processor power limit management

A method and apparatus for accelerated shared data migration between cores. Using an Always Migrate protocol, when a migratory probe hits a directory entry in either modified or owned state, the entry is transitioned to an owned state, and a source done command is sent without sending cache block ownership or state information to the directory.

Method and apparatus for accelerated shared data migration

A method and apparatus for partitioning a cache includes determining an allocation of a subcache out of a plurality of subcaches within the cache for association with a compute unit out of a plurality of compute units. Data is processed by the compute unit, and the compute unit evicts a line. The evicted line is written to the subcache associated with the compute unit.

Cache partitioning

Described are a circuit and a method of analyzing and correcting a fault occurring in operation of the circuit during a power gating sequence. The method includes executing a modification of the power gating sequence that includes maintaining operation of a trace capture buffer (TCB); recording, in the TCB, events occurring during the executing; and correcting the fault based on analysis of the events recorded in the TCB. The circuit includes a plurality of components including a TCB, and a switch configured to maintain power to the TCB in a first state and turn off power to the TCB in a second state.

Method and circuitry for debugging a power-gated circuit

In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer &#x3e;=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.

Command packet packing to mitigate CRC overhead

A system and method for managing multiple discrete operating points to create a stable virtual operating point. One or more functional blocks within a processor produces data corresponding to an activity level associated with the respective functional block. A power manager determines a power consumption value based on the data once every given sample interval. In addition, the power manager determines a signed accumulated difference over time between a thermal design power (TDP) and the power consumption value. The power manager selects a next power-performance state (P-state) based on comparisons of the signed accumulated difference and given thresholds. Transitioning between P-states in this manner while the workload does not significantly change causes the processor to operate at a virtual operating point between supported discrete operating points.

Managing multiple operating points for stable virtual frequencies

A data processing device is disclosed that includes multiple processing cores, where each core is associated with a corresponding cache. When a processing core is placed into a first sleep mode, the data processing device initiates a first phase. If any cache probes are received at the processing core during the first phase, the cache probes are serviced. At the end of the first phase, the cache corresponding to the processing core is flushed, and subsequent cache probes are not serviced at the cache. Because it does not service the subsequent cache probes, the processing core can therefore enter another sleep mode, allowing the data processing device to conserve additional power.

Processor power management and method

In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).

Shared resources in a chip multiprocessor

In one embodiment, a method comprises assigning a unique node number to each of a first plurality of nodes in a first partition of a system and a second plurality of nodes in a second partition of the system. A first memory address space spans first memory included in the first partition and a second memory address space spans second memory included in the second partition. The first memory address space and the second memory address space are generally logically distinct. The method further comprises programming a first address map in the first partition to map the first memory address space to node numbers, wherein the programming comprises mapping a first memory address range within the first memory address space to a first node number assigned to a first node of the second plurality of nodes in the second partition, whereby the first memory address range is mapped to the second partition.

Communicating between partitions in a statically partitioned multiprocessing system

Growing community of inventors

San Jose, CA, United States of America

William Alexander Hughes